82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
19
3.3.6
Power Supplies for the 82541xx Controller
The 82541xx controller requires three power supplies: 1.2 V, 1.8 V, and 3.3 V. The 1.2 V supply
must provide approximately 500 mA current, and the 1.8 V supply, approximately 230 mA current.
The 3.3 V supply must provide only 30 mA current.
A central power supply can provide all the required voltage sources, or the power can be derived
and regulated locally near the Ethernet control circuitry. All voltage sources must remain present
during powerdown in order to use the 82541xx LAN wake up capability. This consideration makes
it more likely that at least some of the voltage sources will be local.
Instead of using external regulators to supply 1.2 V and 1.8 V, power transistors can be used in
conjunction with on-chip regulation circuitry. (See the reference schematic for an implementation
example.)
The 82541xx controller has a LAN_PWR_GOOD input. Treat this signal as an external device
reset which works in conjunction with the internal power-on reset circuitry. In the situation where a
central power supply furnishes all the voltage sources, LAN_PWR_GOOD can be tied to the
POWER_GOOD output of the power supply. Designs that generate some of the voltages locally
can connect LAN_PWR_GOOD to a power monitor chip.
The power sources are all expected to ramp up during a brief power-up interval (approximately
20 ms) with LAN_PWR_GOOD de-asserted. The 82541xx controller must not be left in a
prolonged state where some, but not all, voltages are applied. The 3.3 V source should be powered
up prior to the 1.2 V or 1.8 V sources. The 1.2 V and 1.8 V power supplies may power up
simultaneously. At any time during power up, the supply voltages must be: 1.2 V < 1.8 V < 3.3 V.
3.3.7
82541xx Controller Power Supply Filtering
The 82541xx controller switches relatively high currents at high frequencies, requiring generous
use of both bulk capacitance and high speed decoupling capacitance adjacent to the device.
Bypass capacitors for each power rail should be 0.1 µF. If possible, orient the capacitors close to
the device and adjacent to power pads. Decoupling capacitors should connect to the power and
ground planes with short, thick traces (15 mils or 0.4 mm or more), and 14 mil (3.5 mm) vias per
capacitor pad.
Furnish approximately 20 µF of bulk capacitance for each of the main 1.2 V and 1.8 V levels. This
can be easily achieved by using two 10 µF capacitors, placing them as close to the device power
connections as possible.
3.3.8
82541xx Controller Power Management and Wake Up
The 82541xx Gigabit Ethernet Controller supports low power operation as defined in the PCI Bus
Power Management Specification. There are two defined power states, D0 and D3. The D0 state
provides full power operation and is divided into two sub-states: D0u (uninitialized) and D0a
(active). The D3 state provides low power operation and is also divided into two sub-states: D3hot
and D3cold.
To enter the low power state, the software driver must stop data transmission and reception. Either
the operating system or the driver must program the Power Management Control/Status Register
(PMCSR) and the Wakeup Control Register (WUC). If wakeup is desired, the appropriate wakeup
LAN address filters must also be set. The initial power management settings are specified by
EEPROM bits.
Содержание 82562EX
Страница 42: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide 34 Note This page intentionally left blank...
Страница 44: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide 36 Note This page intentionally left blank...
Страница 68: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide 60 Note This page intentionally left blank...
