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Intel 82562EX, Руководство по конструкции

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82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide

 

41

 

H12

NC

HSDACN

NC

X

NC

NC

NC

H13

MDI[3]+

MDI[3]+

NC

X

Magnetics

Magnetics

Magnetics

10/100 
Magnetics will 
not have a pin 
connected here

H14

MDI[3]-

MDI[3]-

NC

X

Magnetics

Magnetics

Magnetics

10/100 
Magnetics will 
not have a pin 
connected here

J1

PAR

PAR

NC

X

PAR

PAR

PAR

J2

PERR#

PERR#

NC

X

PERR#

PERR#

PERR#

J3

GNT#

GNT#

NC

X

GNT#

GNT#

GNT#

J4

EEMODE

NC

NC

X

Pull-down or 
NC

NC

NC

82541xx: 
Connect a pull-
down for 
Microwire and 
a pull-up for 
SPI* (82541GI/
EI only)

J5

1.2 V

1.5 V

VCCR

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J6

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J7

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J8

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J9

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J10

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J11

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

J12

AUX_PWR

AUX_PWR

NC

X

AUX_PWR

AUX_PWR

AUX_PWR

J13

XTAL_1.8V

HSDACP

NC

X

1.8V

2.5 V

No stuff

PHY Power 
Plane

J14

XTAL2

XTAL2

X2

K1

AD[16]

AD[16]

NC

X

AD[16]

AD[16]

AD[16]

K2

VSS

VSS

VSS

K3

3.3 V

3.3 V

VCC

K4

3.3 V

3.3 V

VCC

K5

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

K6

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

K7

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

K8

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

K9

1.2 V

1.5 V

VCC

X

X

1.2 V

1.5 V

3.3 V

Core Power 
Plane

Table 13.  Ball Number to Signal Mapping (Sheet 5 of 8) (Continued)

Population Options

Ball

Ref

82541xx

Pin

Name

82540EP

Pin Name

82562EZ

Pin Name

D

1

K

2

82541xx

82540EP

82562EZ

Comments

Содержание 82562EX

Страница 1: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide Application Note Networking Silicon 317506 001 Revision 2 9...

Страница 2: ...ctions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The 82...

Страница 3: ...d reference schematics to reflect new Tx and Rx termination values new LAN disable circuit RBIAS100 RBIAS10 values and VIO signaling connection and pullup resistor value 2 3 Nov 2004 Change resistor v...

Страница 4: ...iv 82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide Note This page is intentionally left blank...

Страница 5: ...LC Implementations 12 3 2 5 82562EZ EX Device Test Capability 12 3 3 Designing with the 82541xx Gigabit Controllers 13 3 3 1 82541xx Ethernet Controller LAN Disable Guidelines 13 3 3 2 Serial EEPROM f...

Страница 6: ...Reference Schematic 45 A Measuring LAN Reference Frequency Using a Frequency Counter 53 A 1 Background 53 A 2 Required Test Equipment 53 A 3 Indirect Probing Method 54 A 4 Indirect Frequency Measureme...

Страница 7: ...s 6 5 82562EZ EX Memory Layout 128 Byte EEPROM 12 6 82562EZ EX Memory Layout 512 Byte EEPROM 12 7 82562EZ EX Recommended Magnetics Modules 12 8 Microwire 64 x 16 Serial EEPROMs 15 9 SPI Serial EEPROMs...

Страница 8: ...viii 82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide Note This page intentionally left blank...

Страница 9: ...platform depends on the end user s need for connection speed and manageability As the requirements change footprint compatibility makes it possible to re focus the platform without the need to redesig...

Страница 10: ...Board PCB Design Guide Intel Corporation 82547GI EI 82541GI EI 82541ER EEPROM Map and Programming Information Intel Corporation ICH2 Integrated LAN Controller Function Disable and Power Control Intel...

Страница 11: ...connect to the I O Control Hub 5 ICH5 LCI is a point to point interface optimized to support one device Line termination mechanisms are not specified for the LCI Slew rate controlled output buffers a...

Страница 12: ...slave devices for configuration and register programming After the devices have been properly initialized they can also operate as PCI masters to fetch memory descriptors and to read write data buffe...

Страница 13: ...erally considered to be the mainstay of frequency control components due to their low cost and ease of implementation They are available from numerous vendors in many package types and with various sp...

Страница 14: ...ss fundamental mode oscillation as the circuit powers up Selecting values for these components is beyond the scope of this document 3 1 1 2 Nominal Frequency Intel Ethernet controllers use a crystal f...

Страница 15: ...series resonant and parallel resonant are often used to describe crystal circuits Specifying parallel mode is critical to determining how the crystal frequency is calibrated at the factory A crystal...

Страница 16: ...and the actual load will pull the oscillator slightly off frequency Note C1 and C2 may vary by as much as 5 approximately 1 pF from their nominal values 3 1 1 7 Shunt Capacitance The shunt capacitanc...

Страница 17: ...ders and Associates S A crystal network analyzer is available then discrete crystal components can be tested until one is found with zero or nearly zero ppm deviation with the appropriate capacitive l...

Страница 18: ...hanges Temperature changes can cause the crystal frequency to shift Therefore frequency measurements should be done in the final system chassis across the system s rated operating temperature range 3...

Страница 19: ...that the ICHx Integrated LAN Controller is initialized Figure 3 illustrates a possible solution for ICHx Integrated LAN disable Figure 3 82562EZ EX LAN Disable Circuitry Note The 100 resistors for th...

Страница 20: ...EX PLC device uses a single 3 3 V power supply The 3 3 V supply must provide approximately 90 mA current for full speed operation Standby power must be furnished in order to wake up from powerdown 3...

Страница 21: ...o use the LAN_POWER_GOOD signal for a LAN disable input on the 82541xx device This pin is intended to operate as a power on reset connected to a power monitor circuit The input of the 82541xx FLSH_SO...

Страница 22: ...evice after reset to provide pre boot configuration data before it is accessed by host software The remainder of the EEPROM space is available to software for storing the MAC address serial numbers an...

Страница 23: ...that have been found to work satisfactorily with the 82541xx device are listed in Table 9 SPI EEPROMs must be rated for a clock rate of at least 2 MHz 3 3 3 EEPROM Map Information Table 10 lists the...

Страница 24: ...n place of the crystal with the proper design considerations The clock oscillator has an internal voltage regulator of 1 2 V to isolate it from the external noise of other circuits to minimize jitter...

Страница 25: ...d X2 input signals or a single ended clock input on the X1 pin with common mode biasing of the X2 pin A relatively low drive strength of the 82541GI crystal driver does not guarantee the differential...

Страница 26: ...0 A low capacitance high impedance probe C 1 pF R 500 K should be used for testing Probing the parameters can affect the measurement of the clock amplitude and cause errors in the adjustment A test sh...

Страница 27: ...V source should be powered up prior to the 1 2 V or 1 8 V sources The 1 2 V and 1 8 V power supplies may power up simultaneously At any time during power up the supply voltages must be 1 2 V 1 8 V 3 3...

Страница 28: ...he ICH5 that goes active in response to receiving a Magic Packet a network wake up packet or link status change indication PME remains asserted until it is disabled through the Power Management Contro...

Страница 29: ...for Gigabit operation is very similar to designing for 10 100 Mbps For the 82541xx Gigabit Ethernet Controller system level tests should be performed at all three speeds 4 1 1 Guidelines for Component...

Страница 30: ...erformance 4 1 2 Crystals Crystals should not be placed near I O ports or board edges Radiation from these devices may be coupled onto the I O ports or out of the system chassis Crystals should also b...

Страница 31: ...traces within a differential pair Keep the signal trace lengths of a differential pair equal to each other Do not use serpentines to try to match trace lengths in the differential pair Serpentines cau...

Страница 32: ...icon 4 1 5 Signal Trace Geometry The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane To minimize trace inductanc...

Страница 33: ...de noise can degrade the receive circuit s performance and contribute to radiated emissions 4 1 7 Impedance Discontinuities Impedance discontinuities cause unwanted signal reflections Avoid vias signa...

Страница 34: ...ood grounding requires minimizing inductance levels in the interconnections and keeping ground returns short signal loop areas small and power inputs bypassed to signal return will significantly reduc...

Страница 35: ...the ground planes beneath the transformer minimizes noise coupling between the primary and secondary sides of the transformer and between the adjacent coils in the magnetics This arrangement also impr...

Страница 36: ...ootprint Design Guide 28 Figure 8 Ideal Ground Split Implementation Board Edge RJ Mag Chassis GND RJ Shield connected to Chassis GND Capacitor Stuffing Options Capacitor Stuffing Options Resistive Ter...

Страница 37: ...s and a 1500 pF capacitor This Bob Smith termination scheme is normally contained inside an integrated magnetics module The 75 termination resistors are required to terminate the common mode of the tw...

Страница 38: ...IAS10 549 to 619 and RBIAS100 619 to 649 to reduce the PCB s output amplitude to better meet the IEEE peak to peak center specification For 100Base TX designs the IEEE specification allows a 950 mVpk...

Страница 39: ...itor should be placed as close as possible to the 49 9 resistors using a wide trace Do not vary the suggested component values Be sure to lay out symmetrical pads and traces for these components such...

Страница 40: ...two traces within a differential pair Asymmetry can create common mode noise and distort the waveforms For each component or via that one trace encounters the other trace should encounter the same com...

Страница 41: ...fferential pair are kept close to each other the edge coupling can lower the effective differential impedance by 5 to 20 Short traces will have fewer problems if the differential impedance is slightly...

Страница 42: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide 34 Note This page intentionally left blank...

Страница 43: ...t Design Guide 35 5 0 Design and Layout Checklists The Design and Layout Checklists are in Portable Data Format PDF and available to aid designers via http developer intel com at http www intel com de...

Страница 44: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide 36 Note This page intentionally left blank...

Страница 45: ...PME PME NC X PME PME PME A7 3 3 V 3 3 V 3 3 V A8 AD 30 AD 30 NC X AD 30 AD 30 AD 30 A9 LAN_PWR_ GOOD LAN_PWR_ GOOD NC X Supervisor IC Supervisor IC No stuff A10 SMBCLK SMBCLK NC X SMBCLK SMBCLK SMBCL...

Страница 46: ...BDATA C10 VSS VSS VSS C11 LED1 ACTIVITY ACTIVITY ACTLED X X LED LED LED Same signal different names C12 AVSS VSS VSSA X X VSS VSS VSS AVSS VSSA VSS C13 MDI 0 MDI 0 TDP X X MDI MDI MDI Same signal diff...

Страница 47: ...X X 1 2 V 1 5 V 3 3 V Core Power Plane E12 ANALOG_1 2V 1 5 V VCCT X X 1 2 V 1 5 V 3 3 V Core Power Plane E13 MD 1 MDI 1 RDP X X MDI MDI MDI Same signal different names E14 MDI 1 MDI 1 RDN X X MDI MDI...

Страница 48: ...NALOG_1 8V 2 5 V NC X 1 8V 2 5 V No stuff PHY Power Plane G13 ANALOG_1 2V 1 5 V VCC X X 1 2 V 1 5 V 3 3 V Core Power Plane G14 AVSS VSS VSS X X VSS VSS VSS AVSS VSS H1 STOP STOP NC X STOP STOP STOP H2...

Страница 49: ...X 1 2 V 1 5 V 3 3 V Core Power Plane J9 1 2 V 1 5 V VCC X X 1 2 V 1 5 V 3 3 V Core Power Plane J10 1 2 V 1 5 V VCC X X 1 2 V 1 5 V 3 3 V Core Power Plane J11 1 2 V 1 5 V VCC X X 1 2 V 1 5 V 3 3 V Core...

Страница 50: ...Plane L10 1 2 V 1 5 V 3 3 V X X 1 2 V 1 5 V 3 3 V Core Power Plane L11 VSS VSS VSS X X VSS VSS VSS VSSP VSS L12 JTAG_TMS JTAG_TMS NC X NC NC NC L13 JTAG_TRST JTAG_TRST JTXD 1 X X LCI LCI LCI ICH driv...

Страница 51: ...X AD 7 AD 7 AD 7 N5 AD 4 AD 4 NC X AD 4 AD 4 AD 4 N6 3 3 V 3 3 V VCCA X X 3 3 V 3 3 V 3 3 V VCCA 3 3 V N7 AD 0 AD 0 NC X AD 0 AD 0 AD 0 N8 3 3 V 3 3 V VCCA X X 3 3 V 3 3 V 3 3 V VCCA 3 3 V N9 FLSH_SCK...

Страница 52: ...CH in reset P11 CTRL12 CTRL15 NC X Pwr Regulator Pwr Regulator No stuff Connect to PNP Don t stuff PNP on 82562EZ EX P12 3 3 V 3 3 V VCC X X 3 3 V 3 3 V 3 3 V VCCP 3 3 V P13 SDP 1 SDP 1 JRXD 0 X X LCI...

Страница 53: ...int Design Guide 45 7 0 Dual Footprint Reference Schematic The following pages illustrate a dual purpose 10 100 Mbps and 10 100 1000 Mbps design using the 82562EZ EX Platform LAN Connect device and th...

Страница 54: ...R W H U D V J D O I W X R K W L Z V W Q H Q R S P R F O O V U H O O R U W Q R F I R Q R L W F H O H V Q D J Q L V X Q H K Z 3 J Q L V X I L W Q H Q R S P R F O O D W V Q 3 0 3 J Q L V X I L W Q H Q R...

Страница 55: ...J R O R W G H O O X S H U D V H F D U W Q R H U H K Z H P R V V U R W V L V H U S X O O X S N D H Z U D Q D O S U R 1 H K W H F D I U H W Q H W X R 5 U H O O R U W Q R R W U R U H O O R U W Q R F K W...

Страница 56: ...H Q J D P V U R W L F D S D F H H U K W H V H K 7 1 B 6 6 6 H K W V V R U F D H Y R E D G H W D F R O H U D W L O S V 1 R W H F D O 3 H O X G R P V F L W H Q J D P H K W H K W R W H O E L V V R S V D...

Страница 57: ...1 B 6 6 6 H K W V V R U F D H Y R E D G H W D F R O H U D W L O S V 1 R W H F D O 3 H O X G R P V F L W H Q J D P H K W H K W R W H O E L V V R S V D H V R O F V D H O X G R P V F L W H Q J D P V U R...

Страница 58: ...7 3 5 1 7 1 5 3 2 25 63 7KHVH WKUHH FDSDFLWRUV DFURVV WKH 66 6B 1 WR 1 VSOLW DUH ORFDWHG DERYH WKH PDJQHWLFV PRGXOH 3ODFH DV FORVH DV SRVVLEOH WR WKH PDJQHWLFV PRGXOH 7KHVH WKUHH FDSDFLWRUV DFURVV WKH...

Страница 59: ...U R K V V H F D U W S H H U H O O R U W Q R K W J Q H O H P D V H K W O H W D P L R U S S D 6 5 2 7 8 5 7 1 5 7 7 6 5 6 1 3 3 5 7 6 1 6 3 5 5 2 3 7 9 7 1 6 3 6 5 2 2 6 Q H K Z G H U L X T H U U H Z R...

Страница 60: ...V U H O O R U W Q R F I R Q R L W F H O H V Q D J Q L V X Q H K Z 3 J Q L V X I L W Q H Q R S P R F O O D W V Q 3 0 3 J Q L V X I L W Q H Q R S P R F O O D W V Q 3 0 3 J Q L V X I L W Q H Q R S P R F...

Страница 61: ...counter should be used to measure the transmitter reference frequency or transmitter reference clock If the transmitter reference frequency is more than 20 ppm below the target frequency then the val...

Страница 62: ...probing of the transmitter reference clock The buffered 125 MHz clock will be a 5X multiple of the crystal circuit s reference frequency Figure 11 Different LAN devices may require different register...

Страница 63: ...ound in Appendix B GigConf exe Register Settings for 82541GI EI Devices 5 Determine the center reference frequency as accurately as possible This can be done by taking 30 to 50 different readings usin...

Страница 64: ...arget frequency then the values for C1 and C2 are too small and they should be increased When tests are performed across temperature it may be acceptable for the center frequency deviation to be a lit...

Страница 65: ...or your model of high resolution digital counter make sure it can display 25 0000 MHz with at least four decimal places frequency resolution 4 Ensure the LAN circuits are powered 5 Determine the cente...

Страница 66: ...ppm below the target frequency then the values for C1 and C2 are too big and they should be decreased When tests are performed across temperature it may be acceptable for the center frequency deviatio...

Страница 67: ...the Set Address field on the right side of the screen use the right arrow key 13 Press Enter to select the highlighted value and then use Backspace to clear out the current value 14 Type 4011 for the...

Страница 68: ...82540EP 82541 PI GI EI 82562EZ EX Dual Footprint Design Guide 60 Note This page intentionally left blank...

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