AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note
8
V1.0, 2006-12
3.1
Combining slow-down Mode with Idle Mode
The slow-down mode can be combined with the idle mode (slow-down-idle mode). This
can be done by performing the following sequence:
1. Select the slow-down frequency in the bitfield CMCON.CLKREL.
2. Enter the slow-down mode by setting the bit PMCON0.SD.
3. Activate idle mode by setting the PCON.IDLE mode.
The slow-down-idle mode can be terminated by first exiting from idle mode and then
followed by clearing the bit PMCON0.SD. It will also be terminated by a hardware reset.
3.2
Slow-Down Mode vs. Slow-Down-Idle Mode Current
Measurements
This section illustrates the current measurements taken from XC866-1FR, XC866-4FR,
XC886 and XC888, and shows the effect of the current consumption by the devices in
slow-down mode and slow-down-idle mode. The measurements are tabulated in
From the tables, it can be observed that the amount of current that can be saved in slow-
down mode reduces with the peripheral frequency. This can be seen in the graphical
representations of each table. The peripherals require less power to operate when the
peripheral clock is reduced in slow-down mode. At low frequencies, the current drawn by
the peripherals become relatively constant and therefore less current can be saved when
the peripheral clock speed is further reduced. In any case, the devices draw the least
current at the lowest possible frequency.
The slow-down-idle mode does not necessary draw the least current at the lowest
possible frequency. This can be observed in
(XC888). The effectiveness of the slow-down-idle mode will depend on factors
such as peripheral activities and the operating frequency. It is therefore necessary to
perform measurements manually to determine whether slow-down-idle mode is more
effective than slow-down mode in reducing current consumption.
