AP08056
Power Saving Features
Operating on a Lower Frequency Clock Mode
Application Note
18
V1.0, 2006-12
6
Operating on a Lower Frequency Clock Mode
The normal system clock runs in PLL Mode. The system frequency (f
SYS
) is defined as:
The N factor is selected by the bitfield PLL_CON.NDIV. The P factor is fixed to 1. The K
factor is fixed at 2 for XC866. It can be selected by the bit CMCON.KDIV (protected bit)
for XC886/888. The internal oscillator frequency (f
OSC
) for XC866 is 10 MHz. The internal
oscillator frequency for XC886/888 is 9.6 MHz.
This system frequency is further divided to derive the CPU clock, peripheral clock and
flash clock. By selecting a different clock mode, the system frequency will be changed
and thus affecting all the other clocks of the entire system. The PLL Base Mode and the
Prescaler Mode are two of the other clock modes that can be used to derive the system
frequency. They will be discussed in the following sections.
Note: Flash programming and erasing operations cannot be carried out in PLL
base and prescaler mode. Such operations can only be carried out correctly
when the system clock is running in PLL mode.
f
SYS
N
P K
⋅
------------ f
OSC
⋅
=
