AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note
7
V1.0, 2006-12
3
Reducing Clock Speed (Slow-Down Mode)
The slow-down mode is used to reduce the power consumption by dividing the CPU
clock and the peripherals clock with a programmable factor. The slow-down mode is
activated by setting the bit PMCON0.SD after the programmable factor in the bitfield
CMCON.CLKREL has been selected. The programmable factors may differ for different
XC800 products.
The slow-down mode is terminated by clearing bit PMCON0.SD, which is a protected bit.
It cannot be written directly when the protection scheme is activated. An example below
shows a software example of a XC866 device entering slow-down mode with system
clock reduced by a factor of 32.
SYSCON0 &= 0xFE;//Access standard SFR region (RMAP = 0)
SCU_PAGE = 0x01;//Open SCU page 1
CMCON &= 0xF0; //Clear CLKREL
CMCON |= 0x06; //Select clock divider = fsys/32
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 |= 0x08; //Set SD to enter slow-down mode
PASSWD = 0xA8; //Close access to writing of all protected bits
Similarly, to exit the slow-down mode,
SYSCON0 &= 0xFE;//Access standard SFR region (RMAP = 0)
SCU_PAGE = 0x01;//Open SCU page 1
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 &= 0xF7; //Clear SD to exit slow-down mode
PASSWD = 0xA8; //Close access to writing of all protected bits
Note: Flash programming and erasing operations are not guaranteed in slow-
down mode. Users must exit this mode before carrying out such operations.
