7.2.7
Electrical characteristics SPI timing
Table 18
Electrical characteristics SPI timing
T
j
= -40°C to 150°C;
V
R1VSx
= 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
condition
Number
Min.
Typ.
Max.
CLK_SPI operating
frequency
f
SPI_clk
–
–
10
MHz –
P_7.2.5.22
CLK signal duty cycle
D
SCL
45
50
55
%
–
P_7.2.5.23
CLK_SPI "high" time
t
SPI_wsclkh
45
–
–
ns
–
P_7.2.5.24
CLK_SPI "low" time
t
SPI_wsclkl
45
–
–
ns
–
P_7.2.5.25
CLK_SPI fall time
t
SPI_clkf
–
–
100
ns
f
SPI_clk
< 1 MHz
P_7.2.5.26
CLK_SPI fall time
t
SPI_clkf
–
–
0.1/
f
SPI_clk
ns
f
SPI_clk
≥ 1 MHz
P_7.2.5.27
CLK_SPI rise time
t
SPI_clkr
–
–
100
ns
f
SPI_clk
< 1 MHz
P_7.2.5.28
CLK_SPI rise time
t
SPI_clkr
–
–
0.1/
f
SPI_clk
ns
f
SPI_clk
≥ 1 MHz
P_7.2.5.29
CLK_SPI lead time
t
SPI_lead
100
–
–
ns
–
P_7.2.5.30
CLK_SPI lag time
t
SPI_lag
50
–
–
ns
–
P_7.2.5.31
SPI chip select (SCS)
rise time
t
SPI_csr
–
–
200
ns
t
SPI_lead
= 100 ns P_7.2.5.32
SPI chip select (SCS)
rise time
t
SPI_csr
–
–
0.2 ×
t
SPI_lead
ns
t
SPI_lead
> 100 ns P_7.2.5.33
SPI chip select (SCS)
rise time
t
SPI_csf
–
–
200
ns
t
SPI_lead
= 100 ns P_7.2.5.34
SPI chip select (SCS)
fall time
t
SPI_csf
–
–
0.2 ×
t
SPI_lead
ns
t
SPI_lead
> 100 ns P_7.2.5.35
SPI data input (SDI)
setup
t
SPI_su
10
–
–
ns
–
P_7.2.5.36
SPI data input (SDI)
hold time
t
SPI_hi
10
–
–
ns
–
P_7.2.5.37
SPI data output (SDO)
valid after CLK_SPI
t
SPI_v
–
–
36 + (0.1/
f
SPI_clk
)
ns
C
SDO,load
= 50 pF;
f
SPI_clk
≥ 1 MHz
P_7.2.5.38
SPI data output (SDO)
valid after CLK_SPI
t
SPI_v
–
–
136
ns
C
SDO,load
= 50 pF;
f
SPI_clk
< 1 MHz
P_7.2.5.39
SPI write propagation
delay SDI to SDO
t
SPI_wpd
–
–
35
ns
–
P_7.2.5.40
SPI data output (SDO)
access
t
SPI_a
–
–
50
ns
C
SDO,load
= 50 pF P_7.2.5.41
SPI data output (SDO)
lag
t
SPI_lag
50
–
–
ns
–
P_7.2.5.42
OPTIREG
™
PMIC TLF30681QVS01
Power management IC
Microcontroller interface and supervisory functions
Datasheet
61
Rev. 1.0
2020-04-08
