7.2.2
SPI write access to protected registers
Certain registers are protected against accidental write operations.
Those protected registers are implemented in pairs, where a protected register (for example
to store a configuration request, while an associated read-only register (for example
) is used to store
the currently active configuration.
By default, write access to protected registers is disabled. The status of the protection can be checked using
. Write access must be enabled using the UNLOCK sequence prior to updating the registers.
After completing the register update, the configuration must be activated using the LOCK sequence. This
disables the write access to the protected register and copies the data to the read-only registers.
After the LOCK sequence an internal configuration time of maximum of 60 µs must be considered to ensure that
the new configuration is applied in the device.
Read access to protected configuration registers is always possible. Read operations invert the data.
The device does not support updating a single protected register. The microcontroller must ensure that all
protected registers are configured properly by writing a new value into particular registers and by verifying the
content of unchanged registers.
UNLOCK sequence
An UNLOCK sequence consists of four consecutive key bytes (1: AB
H
; 2: EF
H
; 3: 56
H
; 4: 12
H
) written into the
register. The respective SPI write operations must be atomic, so that they are not interrupted by an
SPI write operation to a different register. Read operations to any register are permitted. The progress of the
UNLOCK sequence can be monitored in the
register where the respective key bit is set for each
correctly written key byte. If an incorrect UNLOCK sequence occurs due to a wrong key or an SPI write operation
to a different address, then the device resets the UNLOCK sequence and clears all key bits. The device sets the
bit and generates an interrupt. The microcontroller must restart the UNLOCK sequence.
LOCK sequence
A LOCK sequence consists of four consecutive key bytes (1: DF
H
; 2: 34
H
; 3: BE
H
; 4: CA
H
) written into the
register. The respective SPI write operations must be atomic, so that they are not interrupted by an SPI write
operation to a different register. Read operations to any register are permitted. The progress of the LOCK
sequence can be monitored in the
register where the respective key bit is set for each correctly
written key byte. If an incorrect LOCK sequence occurs due to a wrong key or an SPI write operation to a
different address, then the device resets the LOCK sequence and clears all key bits. The device sets the
bit and generates an interrupt. The microcontroller must restart the LOCK sequence.
OPTIREG
™
PMIC TLF30681QVS01
Power management IC
Microcontroller interface and supervisory functions
Datasheet
57
Rev. 1.0
2020-04-08
