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TLE5012B
SSC Registers
User’s Manual
86
Rev. 1.2, 2018-02
External Clock Selection:
External clock operation is possible for the interface configurations SSC only, SSC & PWM, and SSC& SPC. To
switch the TLE5012B to external clock, the following procedure is used:
•
Trigger a chip reset by writing a “1” to the AS_RST bit (address 01
H
[0]) via SSC interface
•
Within 120 µs after the reset command, write a “1” to the CLK_SEL bit (address 06
H
[4])
•
After the power-on time (max. 7 ms), read the CLK_SEL bit via SSC interface to confirm that external clock is
selected
Note: If the clock source (CLK_SEL) bit is switched to external clock during operation of the sensor without a reset
it may occur, due to an internal timing conflict, that the switching command is not accepted and the chip
keeps operating on internal clock.
SIL Register
SIL
Offset
Reset Value
SIL Register
07
H
0000
H
Field
Bits
Type
Description
FILT_PAR
15
w
Filter Parallel
Diagnostic function to test ADCs’ filter. If enabled, the raw
X-signal is routed also to the raw Y-signal input of the
filter so SIN and COS signal should be identical.
0
B
filter parallel disabled
1
B
filter parallel enabled (source: X-value)
Reset: 0
B
FILT_INV
14
w
Filter Inverted
Diagnostic function to test ADCs’ filter. If enabled, the X-
and Y-signals are inverted. The angle output is then
shifted by 180°.
0
B
filter inverted disabled
1
B
filter inverted enabled
Reset: 0
B
15
8
7
0
15
15
w
FILT_PA
R
14
14
w
FILT_IN
V
13
11
Res
10
10
w
FUSE_RE
L
9
Res
77
Res
66
w
ADCTV_E
N
5
3
w
ADCTV_Y
2
0
w
ADCTV_X