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TLE5012B
SSC Registers
User’s Manual
77
Rev. 1.2, 2018-02
S_OV
5
ru
Status Overflow
Cyclic check of DSPU overflow. This bit is updated based
on the current angle value and thus the recommendation
is to read it in update mode, if a consistent read-out is
desired. The bit is reset by a normal SSC read-out.
Deactivation via AS_OV.
0
B
No DSPU overflow occurred
1
B
DSPU overflow occurred
Reset: 0
B
S_DSPU
4
r
Status Digital Signal Processing Unit
Check of DSPU, CORDIC and CAPCOM at startup.
Activation in operation via AS_DSPU possible, but only
recommended during application halt and the error will
not show up, since BIST does not set the error flag (only
clears it). Error will only show up, after a watchdog stop
has been triggered and is not cleared with a SSC read-
out, but only with a chip reset.
0
B
DSPU self-test ok
1
B
DSPU self-test not ok, or self test is running
Reset: 0
B
S_FUSE
3
r
Status Fuse CRC
Cyclic CRC check of configuration registers 08
H
to 0F
H
and startup CRC check of configuration fuses. A CRC
error will remain as long as it persists and has not been
read-out over SSC. Deactivation via AS_FUSE. CRC
check is automatically disabled if auto calibration is
active.
Note: When changing the content of one or more
configuration registers in address range 08
H
to 0F
H
,
a new CRC has to be calculated and stored in
register CRC_PAR (address 0F
H
), otherwise CRC
fail will occur. Also see
section
“Enabling and Disabling Autocalibration” for how to
avoid S_FUSE errors in conjuction with
autocalibration.
0
B
CRC ok
1
B
CRC fail
Reset: 0
B
S_VR
2
r
Status Voltage Regulator
Permanent check of internal and external supply
voltages. Error will be signalized as long as it persists and
has not been read out. Deactivation via AS_VR.
0
B
Voltages ok
1
B
V
DD
over voltage; V
DD
-off; GND-off; or V
OVG
; V
OVA
;
V
OVD
too high
Reset: 0
B
Field
Bits
Type
Description