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TLE5012B
Interfaces
User’s Manual
48
Rev. 1.2, 2018-02
5.4
Short PWM Code (SPC)
The Short PWM Code (SPC) is a synchronized data transmission based on the SENT protocol (Single Edge
Nibble Transmission) defined by SAE J2716. As opposed to SENT, which implies a continuous transmission of
data, the SPC protocoll transmits data only after receiving a specific trigger pulse from the microcontroller. The
required length of the trigger pulse depends on the sensor number, which is configurable. Thereby, SPC allows
the operation of up to four sensors on one bus line.
SPC enables the use of enhanced protocol functionality due to the ability to select between various sensor slaves
(ID selection). The slave number (S_NR) can be given by the external circuit of SCK and IFC pin. In case of V
DD
on SCK, the S_NR[0] can be set to 1 and in the case of GND on SCK the S_NR[0] is equal to 0. S_NR[1] can be
adjusted in the same way by the IFC pin. Only one data line to the slaves is necessary, as the length of the trigger
nibble will awake one or the other slaves, as explained in the next paragraph.
Figure 5-12 Example of four slaves connected to a bus with one master with SPC interface
As in SENT, the time between two consecutive falling edges defines the value of a 4-bit nibble, thus representing
numbers between 0 and 15. The transmission time therefore depends on the transmitted data values. The single
edge is defined by a 3 Unit Time (UT, see
) low pulse on the output, followed by the high time defined
in the protocol (nominal values, may vary depending on the tolerance of the internal oscillator and the influence of
external circuitry). All values are multiples of a unit time frame concept. A transfer consists of the following parts
(
):
•
A trigger pulse by the master, which initiates the data transmission
•
A synchronization period of 56 UT (in parallel, a new sample is calculated)
•
A status nibble of 12-27 UT
•
Between 3 and 6 data nibbles of 12-27 UT
•
A CRC nibble of 12-27 UT
•
An end pulse to terminate the SPC transmission
SPC
master
(µC)
Data
SPC
slave 1
(TLE5012B)
IFC (pin #1)
SCK (pin #2)
IFA/SPC (pin #5)
SPC
slave 4
(TLE5012B)
IFC (pin #1)
SCK (pin #2)
IFA/SPC (pin #5)
SPC
slave 3
(TLE5012B)
IFC (pin #1)
SCK (pin #2)
IFA/SPC (pin #5)
SPC
slave 2
(TLE5012B)
IFC (pin #1)
SCK (pin #2)
IFA/SPC (pin #5)
x 0 1 x x x x x x x x x x x x x
x 0 0 x x x x x x x x x x x x x
x 1 0 x x x x x x x x x x x x x
x 1 1 x x x x x x x x x x x x x
STAT
(Status Register)
S_NR bits
STAT
(Status Register)
S_NR bits
STAT
(Status Register)
S_NR bits
STAT
(Status Register)
S_NR bits
GND
GND
GND
V
DD
V
DD
V
DD
GND
V
DD
The low time length of the
Trigger Nibble from the
master defines the specific
slave number