IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

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32 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Table 49. RAM4 – 0x41: Output Divider 3 Control Register Settings
Bits Default Value Name Function
D7 0 i2c_resetb3 Reset Fractional Output Divider 3 (FOD3) circuit when set to 0.
D6 0
en_pi_out_cap<2:0> Factory reserved /unused bits. D5 0
D4 0
D3 0 selb_norm3 0000: FOD3 and OUT3 are not used.
00x1: FOD3 uses clock from PLL and OUT3 uses clock from FOD3.
1100: FOD3 disabled and OUT3 uses clock from OUT2. En_aux2 needs to be 1.
1111: FOD3 uses clock from OUT2 and OUT3 uses clock from FOD3. En_aux2 needs to
be 1.
“int_mode3” sets integer mode for FOD3 (fractional settings will be ignored).
D2 0 sel_ext3
D1 0 int_mode3
D0 1 en_fod3
Table 50. RAM5 – 0x51: Output Divider 4 Control Register Settings
Bits Default Value Name Function
D7 0 i2c_resetb4 Reset Fractional Output Divider 4 (FOD4) circuit when set to 0.
D6 0
en_pi_out_cap<2:0> Factory reserved /unused bits. D5 0
D4 0
D3 0 selb_norm4 0000: FOD4 and OUT4 are not used.
00x1: FOD4 uses clock from PLL and OUT4 uses clock from FOD4.
1100: FOD4 disabled and OUT4 uses clock from OUT3. En_aux3 needs to be 1.
1111: FOD4 uses clock from OUT3 and OUT4 uses clock from FOD4. En_aux3 needs to be
1.
“int_mode4” sets integer mode for FOD1 (fractional settings will be ignored).
D2 0 sel_ext4
D1 0 int_mode4
D0 0 en_fod4