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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Clock Output Configurations Registers
In Clock Output Configuration registers described in the tables below, the CLKx_pwr_sel bits must be configured to match the clock
outputs' supply voltages applied externally. The bits don't adjust the clock output signal swings. CMOSX2 provides two phase-coherent
single ended CMOS outputs while CMOSD provides 2 signals out of phase by 180degree. In Clock2 Output Configuration, bits are for
disabling/enabling clock output/value and slew rate for differential outputs.
Table 108. RAM6 – 0x60: Clock1 Output Configuration
Bits
Default Value
Name
Function
D7
1
CLK1_cfg[2]
These bits give us the output type configuration mode.
For D7, D6, D5 respectively:
(D7, D6, D5) = 000: low-voltage positive/pseudo emitter-coupled logic (LVPECL);
(D7, D6, D5) = 001: CMOS;
(D7, D6, D5) = 010: HCSL33;
(D7, D6, D5) = 011: Low Voltage Differential Signal (LVDS);
(D7, D6, D5) = 100: CMOS2;
(D7, D6, D5) = 101: CMOSD;
(D7, D6, D5)= 110: HCSL25.
D6
0
CLK1_cfg[1]
D5
1
CLK1_cfg[0]
D4
1
clk1_pwr_sel[1:0]
Output Drive Voltage is set by those bits.
D4 D3 = 00 sets 1.8V.
D4 D3 = 10 sets 2.5V.
D4 D3 = 11 sets 3.3V.
D3
1
D2
0
unused bits
Factory reserved unused bits.
D1
1
CLK1_slew[1]
Slew rate control for CMOS single-ended.
D1 D0 = 00 then output slew rate is 0.8*Normal.
D1 D0 = 01 then output slew rate indicates 0.85*Normal.
D1 D0 = 10 then output slew rate indicates 0.9*Normal.
D1 D0 = 11 then output slew rate indicates 1*Normal.
D0
1
CLK1_slew[0]
Table 109. RAM6 – 0x61: Clock1 Output Configuration
Bits
Default Value
Name
Function
D7
0
CLK1_slew_diff[5:0]
Unused register bits.
D6
0
D5
0
D4
0
D3
0
D2
0
SDOE_CLK1
SDOE_CLK1 = 1 causes OUT1 to disable to Hi-Z when disabled with SD/OE pin.
SDOE_CLK1 = 0 causes OUT1 to disable to High/Low when disabled with SD/OE pin.
D1
0
clk1_amuxen2
This bit is used to disable the output value.
Active High (1) to disable output.
D0
1
en_clkbuf1
This bit is used to enable the clock output.
Active High (1) to enable the clock output.
