IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

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55 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Table 110. RAM6 – 0x62: Clock2 Output
Bits Default Value Name Function
D7 0 CLK2_cfg[2] These bits give us the output type configuration mode.
For D7, D6, D5 respectively:
(D7, D6, D5) = 000: low-voltage positive/pseudo emitter-coupled logic (LVPECL);
(D7, D6, D5) = 001: CMOS;
(D7, D6, D5) = 010: HCSL33;
(D7, D6, D5) = 011: Low Voltage Differential Signal (LVDS);
(D7, D6, D5) = 100: CMOS2;
(D7, D6, D5) = 101: CMOSD;
(D7, D6, D5) = 110: HCSL25.
D6 1 CLK2_cfg[1]
D5 0 CLK2_cfg[0]
D4 1
clk2_pwr_sel[1:0]
Output Drive Voltage is set by those bits.
D4 D3 = 00 sets 1.8V.
D4 D3 = 10 sets 2.5V.
D4 D3 = 11 sets 3.3V.
D3 1
D2 0 unused bit Unused Factory reserved bit.
D1 1 CLK2_slew[1] Slew rate control for CMOS single-ended.
D1 D0 = 00 then output slew rate is 0.8*Normal.
D1 D0 = 01 then output slew rate indicates 0.85*Normal.
D1 D0 = 10 then output slew rate indicates 0.9*Normal.
D1 D0 = 11 then output slew rate indicates 1*Normal.
D0 1 CLK2_slew[0]
Table 111. RAM6 – 0x63: Clock2 Output Configuration
Bits Default Value Name Function
D7 0
CLK2_slew_diff[5:0] Unused register bits.
D6 0
D5 0
D4 0
D3 0
D2 0 SDOE_CLK2
SDOE_CLK2 = 1 causes OUT2 to disable to Hi-Z when disabled with SD/OE pin.
SDOE_CLK2 = 0 causes OUT2 to disable to High/Low when disabled with SD/OE pin.
D1 0 clk2_amuxen2
This bit is used to disable the output value.
Active High (1) to disable output.
D0 0 en_clkbuf2
This bit is used to enable the clock output.
Active High (1) to enable the clock output.