IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

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15 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Configuration Register Detail and Functionality Description
Shutdown Function
The shutdown logic offers flexible configuration of shutdown signaling and clock output enable control. The shutdown logic is summarized
in
Table 24 .
When SP bit D1 = 0 in the Shutdown register 0x00 ( Table 25 ), the SD/OE input is active low. When SP bit D1 = 1, SD/OE is active high.
SH bit D0 in the Shutdown register 0x10 ( Table 25 ) configures the SD/OE input's action as either output enable (OE) for the clock outputs
(leaving the PLL running), or full part shutdown. SH bit D1 = 0 for OE function, or 1 for shutdown function.
In shutdown, the part is shut down, differential outputs are driven High/low, and the single-ended LVCMOS outputs are driven low. In
output-disable, individual outputs can be selected to be either Hi-Z or driven high/low, depending on the configuration of the CLKx_OS
and CLKx_OE bits shown in
Table 24 .
0x58 0x058 0x0B2 0x10C 0x166
Output Divider 4 Step Spread Configuration Register
0x59 0x059 0x0B3 0x10D 0x167
Output Divider 4 Spread Modulation Rate Configuration Register
0x5A 0x05A 0x0B4 0x10E 0x168
Output Divider 4 Spread Modulation Rate Configuration Register
0x5B 0x05B 0x0B5 0x10F 0x169
Output Divider 4 Skew Integer Part
0x5C 0x05C 0x0B6 0x110 0x16A
Output Divider 4 Skew Integer Part
0x5D 0x05D 0x0B7 0x111 0x16B
Output Divider 4 Integer Part
0x5E 0x05E 0x0B8 0x112 0x16C
Output Divider 4 Integer Part
0x5F 0x05F 0x0B9 0x113 0x16D
Output Divider 4 Skew Fractional Part
0x60 0x060 0x0BA 0x114 0x16E
Clock 1 Output Configuration
0x61 0x061 0x0BB 0x115 0x16F
Clock 2 Output Configuration
0x62 0x062 0x0BC 0x116 0x170
Clock 1 Output Configuration
0x63 0x063 0x0BD 0x117 0x171
Clock 2 Output Configuration
0x64 0x064 0x0BE 0x118 0x172
Clock 1 Output Configuration
0x65 0x065 0x0BF 0x119 0x173
Clock 2 Output Configuration
0x66 0x066 0x0C0 0x11A 0x174
Clock 1 Output Configuration
0x67 0x067 0x0C1 0x11B 0x175
Clock 2 Output Configuration
0x68 0x068 0x0C2 0x11C 0x176
CLK_OE/Shutdown Function
0x69 0x069 0x0C3 0x11D 0x177
CLK_OS/Shutdown Function
Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3
Summary (Cont.)
Register Address
Function
RAM CFG0 CFG1 CFG2 CFG3