IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

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3 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
User Configuration Table Selection
At power-up, the voltage at OUT0_SEL_I2CB pin 24 is latched by the part and used to select the state of SEL0/SCL pin 9 and SEL1/SDA
pin 8 (
Table 2 ).
If a weak pull-up (10k Ω ) is placed on OUT0_SEL_I2CB, the SEL0/SCL and SEL1/SDA pins will be configured as hardware select inputs,
SEL0 and SEL1. Connecting SEL0 and SEL1 to VDDD and/or GND selects one of 4 configuration register sets, CFG0 through CFG3,
which is then loaded into the non-volatile configuration registers to configure the clock synthesizer.
If a weak pull-down is placed on OUT0_SEL_I2CB (or if it is left floating to use internal pull-down), the pins SEL0 and SEL1 will be
configured as a I
2
C interface's SDA and SCL slave bus. Configuration register set CFG0 is always loaded into the non-volatile
configuration registers to configure the clock synthesizer. The host system can use the I
2
C bus to update the non-volatile configuration
registers to change the configuration, and to read status registers.
I
2
C Interface and Register Access
When powered up in I
2
C mode ( Table 2 ), the device allows access to internal RAM registers ( Table 4 ). The OTP registers ( Table 3 ) are
programmed by loading the desired values into the RAM registers that shadow the target OTP registers ( Table 4 ), and initiating the
internal programming sequence for the desired register range.
Users should not write to the Trim RAM in address range 0x01–0x0F, or the Test RAM in address range 0x6A–0x6F, and should only write
to the OTP Control in address range 0x70–0x7F when programming the OTP.
The RAM in address range 0x80–0x8F is not used by the device and may be used for any purpose.
Table 2. Power-Up Setting of Hardware Select Pin vs I
2
C Mode, and Default OTP Configuration Register
OUT0_SEL_I2CB Strap at
Power-Up
SEL1/SDA pin SEL0/SCL pin Function
10k Ω pull-up
0 0 OTP bank CFG0 used to initialize RAM configuration registers.
0 1 OTP bank CFG1 used to initialize RAM configuration registers.
1 0 OTP bank CFG2 used to initialize RAM configuration registers.
1 1 OTP bank CFG3 used to initialize RAM configuration registers.
10k Ω pull-down or floating SDA SCL
I
2
C bus enabled to access registers.
OTP bank CFG0 used to initialize RAM configuration registers.
Table 3. OTP Register Map Summary
Register Range OTP Register Block Name Register Block Description
0x000 OTP Control OTP burned status & I²C address setting.
0x001–0x00F Trim Presets Program default settings. See page 6.
0x010–0x069 CFG0 User configuration settings bank 0.
0x06A–0x0C3 CFG1 User configuration settings bank 1.
0x0C4–0x11D CFG2 User configuration settings bank 2.
0x11E–0x177 CFG3 User configuration settings bank 3.
0x178–0x1AF Factory Use Factory settings–do not over-program.