IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

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20 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Figure 3. PLL Pre-Divider Options
If pre-divider is selected by selecting bypass_ prediv = 0 ( Table 31 ) then user can select divider by 2 or divider values from 3 to 127.
Table 31. RAM1 – 0x15: Reference Divider Register
Bits Default Value Name Function
D7 0 Sel_prediv2
Select the divider by 2 function; Divide by 2 if set to 1. And if bypass is set to 0. If divide bit
set 0 and bypass bit set to 0 then reference divider bits (D6 to D0) will take effect.
D6 0
Ref_div[6:0]
Reference Divider value.
Use Ref_div setting for values 3 to 127.
Use bit D7 for divide by 2.
Use “Bypass_prediv” bit in Table 32 for divide by 1.
When “Bypass_prediv” is 1, register 0x15 setting is don't care.
When “Sel_prediv2” is 1, Ref_div[6:0] setting is don't care.
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 32. RAM1 – 0x16: VCO Control Register and Pre-Divider
Bits Default Value Name Function
D7 1 Bypass_prediv
Use D7 = 1 when phase frequency detector needs to be equal to the reference clock.
Use D7 = 0 when the reference clock needs to be divided by at least 2 for the phase
frequency detector. See
Table 31 settings.
D6 0 dither_gain_cfg[2]
Dither gain settings:
Factory reserved bits.
Use default values.
D5 0 dither_gain_cfg[1]
D4 0 dither_gain_cfg[0]
D3 1 afc_en Open loop vco control is enabled if 1 and disabled if 0–factory reserved bit.
D2 1
cnf_afc[2:0] Open loop vco control voltage bits–factory reserved bits. Use default values. D1 0
D0 0