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Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
6. Ensure the “Program/Configure” check box is selected for the Stratix III device file.
7. Select Start.
The Stratix III device will be programmed.
Software can be downloaded and executed only when the FPGA hardware load is programmed. To
download and execute the software load, complete the following:
1. Select “Run” from the “Run” pull-down menu.
This displays up the “Create, manage, and run configurations” dialog window.
2. Select the “Nios II Hardware” option in the dialog window, and then select the “New Hardware
Configuration” button in the upper left-hand corner of the dialog box.
This creates a hardware configuration named “New Configuration” below the “Nios II Hardware”
heading.
3. Select the “New Configuration” item that was just created.
4. In the “SOPC Builder System PTF File” entry text box, use the “Browse” button to select the PTF
file associated with the FPGA hardware configuration you have programmed. The
“srio_1250_x4_sys.ptf” file is found in the same directory as the “srio_1250_x4.sof” hardware
configuration file.
5. In the “Project” text box, select “Browse” and then select the software project name
(srio_1250_x4) which matches the FPGA hardware load.
When the software project is selected, the “NIOS II ELF Executable” text box is filled in with
“srio_test.elf”.
6. Change the name of the configuration from “New Configuration” to a unique hardware/software
configuration name, such as “srio_1250_x4_config”.
7. Select “Run”.
The software is downloaded, and begins execution. Once the software/hardware configuration has
been created, the configuration can be selected to execute or debug the software load.
2.2.3
FPGA Hardware Load Facilities
The FPGA hardware load has the following facilities:
•
RapidIO packet sink memory, 16 KB in size, connected to the RapidIO Avalon Master
1
. The
packet sink memory is the target for NREAD and NWRITE RapidIO request packets received by
the FPGA. The NIOS II processor accesses the RapidIO packet sink memory using the Remote
Read DMA engine or the Remote Write DMA engine.
•
A Remote Read DMA engine, connected to the 16 KB RX_MEMORY. The Remote Read DMA
engine is used to generate NREAD requests. Addresses and packet types are controlled by the
RapidIO Avalon Slave configuration
1
. The processor can access RX_MEMORY starting at address
0x80000.
1. For more information on the RapidIO Avalon Master or Slave, see the
RapidIO MegaCore Function User Guide
available at
www.altera.com.