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Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
1.3.2.7
FPGA Configuration
•
Configuration mode: Active serial and JTAG
•
Serial configuration device: EPCS64, 3.3V, 67 Mb, 16-pin SOIC
•
Dedicated header support USB blaster programming cable
•
Dedicated JTAG port for FPGA JTAG configuration and debugging
•
Voltage: 3.3V
1.3.3
DSP Block
The DSP block includes TI TCI6488 DSP, DDR2 memory, antenna interface, sRIO links, serial flash,
GigE link, and JTAG emulation port (see
Figure 5
). The TI TCI6488 is the major baseband processing
engine on the Tsi620 evaluation board.
1.3.3.1
TCI6488 DSP
•
DSP core: Triple C64X+
•
Core frequency: 983 MHz (61.44Mx16)
•
Core PLL multiplier: 4 ~ 16
•
Core reference clock: 61.44 MHz
•
Cache: L1-64 KB, L2-3 MB
•
Boot mode: I2C, EMAC, sRIO
•
16-bit GPIO assignment:
— 4 bits to FPGA
— 4 bits to Tsi620 through AFS600
— 1 bit to PrPMC for interrupt
— 1 bit to AFS600 for status report
— 6 bits for DSP local configuration
•
Package: 561-pin, 23 x 23 mm BGA with 0.8 mm pitch
•
Voltage supply: core-1.1V SerDes-1.1V, IO-1.8V
•
Power consumption: max 8W
•
Thermal dissipation management: Passive heat-sink, core voltage auto-scaling