45
Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
[/root/linux-2.6.26-rio] cp config.rio .config
[/root/linux-2.6.26-rio] make
2.1.4.2
Modifying the Tsi620 Driver
The Tsi620 low-level driver is not included in the Linux kernel source code because it is not licensed
under the GPL. To compile the binary kernel module, first compile the kernel as described above.
Uncompress the Tsi620 driver into a location of your choice and — from the Linux kernel source
directory — run “make SUBDIRS=<location> modules” with the same environment settings.
Example:
[/root/linux-2.6.26-rio] cd ..
[/root] tar -xjf tsi620.tar.bz2
[/root] cd linux-2.6.26-rio
[/root/linux-2.6.26-rio] make SUBDIRS=../tsi620 modules
2.1.4.3
Modifying the User Space Files
Modifying the user space files on the ramdisk can be done by uncompressing the rImage.gz file
included on the disc, and mounting it at as a loopback device on a Linux system. Files can then be
revised as if they were on the local filesystem. Please note that if installing any programs onto the
ramdisk, they should be compiled using static libraries, or appropriate shared libraries should be
installed. After modifications to the ramdisk are done, unmount the filesystem, gzip it and create a
U-Boot ramdisk image using
mkimag
e program included with the Linux source code (for example,
mkimage -A ppc -O linux -T ramdisk -C gzip -d rImage.gz
rImage.gz.img
).
2.2
FPGA Software
The FPGA software consists of the following:
•
FPGA hardware loads based on the Altera NIOS II Processor and RapidIO IP for each RapidIO
configuration
•
Software loads for the NIOS II processor, specific to each FPGA hardware load
Currently, the only RapidIO configuration available for the FPGA is a four-lane configuration
operating at 62.5 MHz DDR. This is the equivalent of a RapidIO port operating in 4x mode at
1.25 Gbaud. For this reason, the FPGA load is named “altera_stratic_3_srio_1250_x4.zip”.
All examples assume the use of the “altera_stratic_3_srio_1250_x4.zip” load.
The loads available are found in the following zip files:
•
altera_stratix_3_srio_1250_x1.zip - Single lane RapidIO interface, operating at 62.5 MHz DDR
•
altera_stratix_3_srio_2500_x1_zip - Single lane RapidIO Interface, operating at 125 MHz DDR
The installation, configuration and execution of the different software loads is identical.