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Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
Table 7
summarizes the clocking sources requirements for all major components on the Tsi620
evaluation board.
1.3.5.2
Clocking Architecture Implementation
There are two clock synthesizers on board that provide the reference clocking required for the FPGA,
DSP, and sRIO switch. The first synthesizer has a 25-MHz crystal source: it outputs 156.25 MHz with
LVPECL logic to serve sRIO system reference clock, FPGA EMAC and SGMII reference, and DSP
sRIO and SGMII reference. The second clock synthesizer has a 30.72-MHz oscillator source: it
supplies 30.72 MHz and 61.44 MHz CML clocking references for the DSP, DDR2, FPGA antenna
interface, DSP core PLL, and DSP antenna interface (see
Figure 8
).
In order to simplify the clocking architecture, both the DSP core frequency and the on-board DDR2
memory operation frequency, run at slightly lower than their maximum specification. Both DSP and
DDR2 memory use the same clocking source at 61.44 MHz, DSP core frequency is 983 MHz, and
DDR2 memory operates at 614.4 M double data rate.
Table 7: Clocking Sources List
Clock Name
Function/Domain
Logic Standard
Frequency
Input Jitter
SCLK(p,n)
Tsi620 system
reference
LVDS/PECL(AC)
156.25 MHz
SP6_RXCLK
Tsi620 XGMAI RXCLK
HSTL-1.5V
62.5 MHz, 125 MHz,
156.25 MHz
175 ps (pk2pk)
PCI_CLK
Tsi620 PCICLK input
PCI-3.3V
66.7 MHz/33.3 MHz
+/-100 ps
RIO_XGMII_RxCLK
FPGA XGMII RxCLK
input from Tsi620
HSTL-1.5V
62.5 MHz, 125 MHz,
156.25 MHz
GigE_REFCLK
FPGA GigE EMAC
reference
LVDS/PECL(AC)
156.25 MHz
AIF_REFCLK
FPGA OBSAI/OPRI
reference
LVDS/PECL(AC)
30.72 MHz
SYSCLK{p,n}
DSP core and AIF
reference
LVDS/PECL(AC)
61.44 MHz
2 ps RMS
DDRREFCLK(p,n)
DSP DDR2 reference
LVDS/PECL(AC)
61.44 MHz
75 ps (pk2pk)
RIOSGMIICLK(p,n)
DSP sRIO and SGMII
reference
LVDS/PECL(AC)
156.25 MHz
4 ps RMS
56 ps (pk2pk)
GigE PHY_REFCLK
GigE PHY
Crystal
25 MHz
AFS600_REFCLK
AFS600 reference
clock
Internal RC
100 MHz +/-1%