11
Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
1.2.2.7
Clocking Distribution
•
On-board clock generation and distribution for sRIO domain, GigE domain, and OBSAI domain
•
On-board clock generation and distribution for FPGA, DSP, and Tsi620
•
SMT connectors for the base station system frame synchronization
•
AMC backplane system clocking synchronization
1.2.2.8
Board System Controller
•
Actel Flash-based FPGA, AFS600-FBGA256
•
Board reset control
•
Power sequence control and monitoring
•
Board status report
•
AMC MMC support
•
Multiple voltage interface conversion
1.2.2.9
Power Management
•
Meets AMC.0 specification for power management
•
12V power supply from AMC finger connector
•
12V@5A DC input connector for stand-alone operation
•
60W maximum power consumption including PrPMC module
•
3.3V@100mA for AMC management power
1.2.3
Board Architecture
Figure 2
displays the architecture of the Tsi620 evaluation board. The board includes the following
functional blocks; each block’s architectural features are discussed in the next section (see
“Board
Hardware Functional Description”
):
•
sRIO switching and PrPMC module
•
Stratix3 FPGA block
•
TCI6488 DSP block
•
GigE interface
•
Clocking distribution
•
Power management
•
System controller
•
AMC backplane and front panel connectors