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Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
1.5.1.3
S3 – MISC Setting
1.5.1.4
S4 – Tsi620 Option Setting
1.5.1.5
S5 – DSP Clocking Setting
Table 11: S3[1:2:3:4] Setting
Switch S3
Signal Assignment
Default
ON/OFF Setting
Bit 1
PCI_M66EN
1 = OFF
ON = Force PCI bus clock at 33 MHz
OFF = Set PCI bus clock at 66 MHz
Bit 2
Tsi620_BCE
1 = OFF
ON = Set Tsi620_BCE to “0” for on-die-scope operation
OFF = Normal operation
Bit 3
FPGA_SET_3V3
1 = OFF
ON = 0 or logic low to FPGA
OFF = 1 or logic High to FPGA
Bit 4
AFS_SET_3V3
1 = OFF
Reserved
Table 12: S4[1:2:3:4] Setting
Switch S4
Signal Assignment
Default
ON/OFF Setting
Bit 1
TSI620_SP_HOST
1 = OFF
ON = Force PCI bus clock at 33 MHz
OFF = Set PCI bus clock at 66 MHz
Bit 2
TSI620_I2C_DISABLE
1 = OFF
ON = Set Tsi620_BCE to 0 for on-die-scope operation
OFF = Normal operation
Bit4_Bit3
TSI620_SP_IO_
SPEED[1:0]
1_0
OFF_ON
0_0 = 1.25 Gbps sRIO link
0_1 = 2.5 Gbps sRIO link
1_0 = 3.125 Gbps sRIO link
1_1 = Reserved
Table 13: S5[1:2:3:4] Setting
Switch S5
Signal Assignment
Default
ON/OFF Setting
Bit 1
CORECLKSEL
1 = OFF
ON = Force PCI bus clock at 33 MHz
OFF = Set PCI bus clock at 66 MHz
Bit 2
FPGA_SET_1V8
1 = OFF
ON = 0 or logic low to FPGA
OFF = 1 or logic high to FPGA
Bit4_Bit3
30M72_SEL[0:1]
0_0
ON_ON
0_0: On-board 30.72 MHz oscillator
0_1: 30.72 MHz from AFS600
1_0: 30.72 MHz from FPGA
1_1: External 30.72 MHz clock from SMA J13