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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
DPLL_CTRL_0.DPLL_FOD_FREQ
DPLL FOD frequency is determined by M / N.
DPLL_CTRL_0.DPLL_FINE_PHASE_ADV_CFG Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description
RESERVED
N/A
-
This field must not be modified from the read value
FINE_PHASE_ADVANCE[
12:0]
R/W
0
Unsigned (i.e. positive) 13-bit fine phase advance.
Note: This register must be set to 0 if the DPLL feedback clock has a fractional
component.
Resolution is in units of input TDC period/4096. The default input TDC clock is
625 Mhz, so the default input TDC period is 1.6 ns which results in a resolution
of approximately 391 fs.
Ex. 0x0002 translates to 782 fs (0.782 ps) phase advance applied to the DPLL.
Conversely, 0x0000 means no phase advance is applied to the DPLL.
Note: Phase advance is defined as the phase of the output that is measured
relative to another reference and the output clocks rising edge comes after the
rising edge of the reference signal, by some amount X, then a phase advance
on the output clock will result in a measurement of X - fine_phase_advance.
Note: The DPLL fractional feedback clock frequency correction is lost when a
non zero phase advance is applied. To restore previous DPLL configuration,
need to set 'fine_phase_advance' to 0 and re-trigger the DPLL configuration.
Table 268: DPLL_CTRL_0.DPLL_FOD_FREQ Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_CTRL_0.DPLL_FOD_FREQ Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
01Ch
M[7:0]
01Dh
M[15:8]
01Eh
M[23:16]
01Fh
M[31:24]
020h
M[39:32]
021h
M[47:40]
022h
N[7:0]
023h
N[15:8]