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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET
Phase pull-in offset.
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_SLOPE_LIMIT
Phase pull-in slope limit.
Table 297: DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
000h
DPLL_PHASE_PULL_IN_OFFSET[7:0]
001h
DPLL_PHASE_PULL_IN_OFFSET[15:8]
002h
DPLL_PHASE_PULL_IN_OFFSET[23:16]
003h
DPLL_PHASE_PULL_IN_OFFSET[31:24]
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description
DPLL_PHASE_PULL_IN_
OFFSET[31:0]
R/W
0
Signed 32-bit phase pull-in offset in nanoseconds.
The phase offset for the phase pull-in operation.
Table 298: DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_SLOPE_LIMIT Bit Field Locations and
Descriptions
Offset
Address
(Hex)
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_SLOPE_LIMIT Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
004h
DPLL_PHASE_PULL_IN_SLOPE_LIMIT[7:0]
005h
DPLL_PHASE_PULL_IN_SLOPE_LIMIT[15:8]
006h
DPLL_PHASE_PULL_IN_SLOPE_LIMIT[23:16]
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_SLOPE_LIMIT Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description
DPLL_PHASE_PULL_IN_
SLOPE_LIMIT[23:0]
R/W
0
Unsigned 24-bit max FFO in ppb.
The maximum FFO value for calculating phase pull-in time. This value should
not exceed 244000 ppb. Value 0 implies that the maximum FFO 244000 ppb will
be applied.