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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
DPLL_0.DPLL_WRITE_PHASE_TIMER
Write phase timer.
DPLL_0.DPLL_PRED_CFG
Predefined configuration selection.
DPLL_0.DPLL_WRITE_FREQ_TIMER Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description
WRITE_FREQ_TIMEOUT_
CNFG[15:0]
R/W
0
Unsigned 16-bit write frequency timeout value in milliseconds.
When in write frequency mode, the DPLL_WR_FREQ must be periodically
written to within WRITE_FREQ_TIMEOUT_CNFG ms.
If the write frequency timer expires, the write frequency as a reference is
disqualified. Upon disqualification, depending on the configuration, a reference
switch may occur the DPLL may enter the configured holdover mode.
Value 0 implies no timeout.
Table 212: DPLL_0.DPLL_WRITE_PHASE_TIMER Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_0.DPLL_WRITE_PHASE_TIMER Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
02Eh
WRITE_PHASE_TIMEOUT_CNFG[7:0]
02Fh
WRITE_PHASE_TIMEOUT_CNFG[15:8]
DPLL_0.DPLL_WRITE_PHASE_TIMER Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description
WRITE_PHASE_TIMEOU
T_CNFG[15:0]
R/W
0
Unsigned 16-bit write phase timeout value in milliseconds.
When in write phase mode, the DPLL_WRITE_PH must be periodically written
to within WRITE_PHASE_TIMEOUT_CNFG ms.
If the write phase timer expires, the write phase as a reference is disqualified.
Upon disqualification, depending on the configuration, a reference switch may
occur the DPLL may enter the configured holdover mode.
Value 0 implies no timeout.
Table 213: DPLL_0.DPLL_PRED_CFG Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_0.DPLL_PRED_CFG Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
030h
RESERVED[7:2]
WP_PRED[1] PRED_EN[0]