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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
PLL Fractional Feedback Divider and Loop Filter
Only use the 12-bit integer portion of the PLL Feedback Divider M. The setting FB_intdiv[11:0] is spread out over 2 registers.
The value of M is FVCO / FREF2PLL and care must be taken that M is an integer value.
Example
: The circuit uses a 25MHz crystal and we want the VCO to be 2500MHz.
The value of M needs to be 2500 / 25 = 100.
FB_intdiv[11:0] = DEC2HEX(100) = 0 64 or 0000 0110 0100 binary.
Table 33. RAM1 – 0x11: VCO Band and Factory Reserved Bits
Bits
Default Value
Name
Function
D7
1
unused
Unused Factory reserved bit.
D6
1
unused
Unused Factory reserved bit.
D5
0
test_mode_vco_band
“test_mode_vco_band” is 1 enables the VCO test mode.
D4
0
vco_band[4:0]
When bit D5 is 1, it forces the VCO to use the VCO band value in bits D0–4 and ignore
the VCO band (auto) calibration.
D3
1
D2
1
D1
0
D0
0
Table 34. RAM1 – 0x17: Feedback Integer Divider Register
Bits
Default Value
Name
Function
D7
0
FB_intdiv[11:4]
The Feedback Integer Divider Register has 12 bits spread on 2 registers 0x17 and 0x18.
D6
0
D5
0
D4
0
D3
0
D2
1
D1
1
D0
1
