IDT 5P49V6965, Руководство по описанию регистров и программированию

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30 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Figure 6. Output Divider Control Settings Block Diagram
There are a number of MUX circuits to route clocks around and/or through certain fractional output dividers. For example, the output from
FOD1 can be channeled to outputs 1 through 4 so only FOD1 needs to be enabled when all output frequencies are the same. There are
also channeling options to use the output of one FOD to be the input of the following FOD so the output of that second FOD can be a very
low frequency, for example a few kHz. Only when an FOD gets its input clock from the PLL can the fractional part of the divider be used.
When using the clock from a previous output, the FOD can only be used in integer mode. The following pages explain how to set up the
MUX.
Table 46. FOD1 Register Table
Register Offsets
Output (MHz) 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2C 0x2E 0x2F
97.1455 5 A5 3E DC 00 00 00 00 00 00 00 0 D0 00
98.147 5 0E A9 54 00 00 00 00 00 00 00 0 D0 00
99.1485 4 7B 1E 90 00 00 00 00 00 00 00 0 D0 00
100.15 3 EA 87 38 00 00 00 00 00 00 00 0 D0 00
101.1515 3 5C CC DC 00 00 00 00 00 00 00 0 D0 00
102.153 2 D1 D9 E8 00 00 00 00 00 00 00 0 D0 00
103.1545 2 49 99 A8 00 00 00 00 00 00 00 0 D0 00
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
V
DDD
V
DDO
0
OUT0_SEL_I2CB
V
DDO
1
OUT1
OUT1B
V
DDO
2
OUT2
OUT2B
V
DDO
3
OUT3
OUT3B
V
DDO
4
OUT4
OUT4B
FOD1
FOD2
FOD3
FOD4
PLL
OTP
and
Control
Logic
en_clkbuf1
0
1
0
1
0
1
0
1
en_clkbuf2
en_clkbuf3
en_clkbuf4
en_fod4
en_fod3
en_fod2
en_fod1
en_refmode
en_aux1
en_aux2
en_aux3
sel_ext1, selb_norm1,
int_mode1
sel_ext2,
selb_norm2,
int_mode2
sel_ext3,
selb_norm3,
int_mode3
sel_ext4,
selb_norm4,
int_mode4