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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Skew
Skew is not implemented with a parallel load of the count of the output divider as is commonly done with non-fractional divides. Instead
skew is accomplished by increasing the value of the fractional output divider for only the very first clock cycle. The divide is increased by
the number of VCO cycles required to delay the completion of the first output clock cycle by the desired skew. For the second and all
subsequent output cycles, hardware changes the output divider to the value for the proper steady state output frequency.
The integer and fractional components of skew are calculated as follows:
There are 12 bits for an integer value and 6 bits for a fraction. The unit used for the skew is degrees of delay of the edge.
The VCO frequency is first divided by 2 before it goes to the Output Divider. The number programmed for skew is the amount of cycles of
the VCO/2 frequency that is needed to achieve the skew amount.
Let's use an example of OUT1 = 100MHz, OUT2 = 100MHz and we want to delay OUT1 with 1.3ns versus OUT2. The total cycle is 10ns
so 1.3ns represents 360×1.3/10 = 46.8° of skew. Let's also say that we used VCO = 2800MHz so the Output Divider value N =
(2800/2)/100 = 14. Each cycle of the VCO/2 = 1400MHz signal represents 360/14 = 25.7°. That means the skew number will be 46.8/25.7
= 1.82. The integer part of the skew will be 1 and the fractional setting will be INT(0.82×2
6
) = 116 or 74 hex.
The formulas for skew are as follows:
Formula for the integer value:
Formula for the fraction:
INT (Skew) = INT((1+46.8/360)*14) - INT(14) = 15 - 14 = 1.
FRAC (Skew) = (1+46.8/360)*14 - INT(14) - 1 = 0.82.
Translating these two values to register settings:
= 74 (hex)
= 001 (hex)
