IDT 5P49V6965, Руководство по описанию регистров и программированию

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29 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Example of FOD calculation for SSCE = 1
Out1 of clock1 = 99MHz, spread enabled with total spread 0.5% and SS 31.5KHz.
Feedback divider = 112.4, and VCO = 2810MHz. Let's calculate the FOD 1 value according to the equations above.
F
VCO
/2 = 2810/2 = 1405, and FOUT = 99MHz (given).
(F
VCO
/2)/ FOUT = 1405/99 = 14.19191919.
OD1 Integer = 14 then ODx_intdiv[11:0] = E.
As ssce = 1, ODx_period(dec) = (½) * (FOUT / FSS).
Fss = 31.5kHz and Fout = 99MHz then ODx_period(dec) = 1571.42857143.
Now, from Eq.6 , ODx_period [12:0] = 623.
From Eq.7 , ODx_Step(dec) = [((0.5/100)*(14.19191919)] / 1571 = 0.00004516842.
From Eq.8
→
(0.00004516842 * 2
24
) = 757.800338719 then Odx_Step [23:0] = 2F5.
From Eq.9 , ODx_offset(dec) = 0.19191919 - ((0.5 / 100) * 14.19191919)/ 2] = 0.15643939.
From Eq.10 , (2
24
* 0.15643939) = 2624617.502
→
Odx_offset [29:0] = 280C69.
Some calculated examples with SSCE = 0 for frequency margining purposes:
Table 44. Table for PLL Configured Values
input clock (MHz) 25
ref_div (real) 0
ref_div (Hex) 0
bypass_pre_div 1
Ref for PLL (MHz) 25
VCO (GHz) 2.8
FB_div (real) 112
FB_intdiv (Hex) 70
FB_frcdiv (Hex) 0
Table 45. Output Values with SSCE = 0
Frequency
Margining
Output
(MHz) ssce
Divider
(real)
out_intdiv
(HEX)
Period
(Hex)
Step
(real)
Step
(HEX)
Offset
(real)
Offset
(HEX)
skew_int
(HEX)
skew_frac
(HEX)
-3% 97.1455 0 14.41137 D 0 0 0 1.411373 1694FB7 1 0
-2% 98.147 0 14.26432 D 0 0 0 1.264318 143AA55 0 0
-1% 99.1485 0 14.12023 D 0 0 0 1.120234 11EC7A4 0 0
0% 100.15 0 13.97903 D 0 0 0 0.979031 FAA1CE 0 0
1% 101.1515 0 13.84063 D 0 0 0 0.840625 D73337 0 0
2% 102.153 0 13.70493 D 0 0 0 0.704933 B4767A 0 0
3% 103.1545 0 13.57188 D 0 0 0 0.571875 92666A 0 0