Rev. 1.10
92
November 04, 2019
Rev. 1.10
93
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
There is an internal analog signal derived from 20×A2P, which can be connected to the A/D converter
as the analog input signal by configuring the SAINS2~SAINS0 bits. If the external channel input
is selected to be converted, the SAINS2~SAINS0 bits should be set to “000” or “101~111” and the
SACS3~SACS0 bits can determine which external channel is selected. If the internal analog signal
is selected to be converted, the SACS3~SACS0 bits must be configured with a value from 1010 to
1111 to switch off the external analog channel input. Otherwise, the internal analog signal will be
connected together with the external channel input. This will result in unpredictable situations.
SAINS[2:0] SACS[3:0] Input Signals
Description
000,
101~111
0000~1001
AN0~AN9
External pin analog input
1010~1111
—
Floating, no external channel is selected
001
1010~1111
20×A2P
20 times OPA2 positive input voltage signal
010~100
1010~1111
—
Unused, connected to ground
A/D Converter Input Signal Selection
A/D Converter Operation
The START bit in the SADC0 register is used to start the A/D conversion. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an
A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be
cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be
generated. This A/D internal interrupt signal will direct the program flow to the associated A/D
internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller
can poll the ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative
method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
SYS
, can be chosen
to be either f
SYS
or a subdivided version of f
SYS
. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the
system clock f
SYS
and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D
clock source speed that can be selected. As the recommended range of permissible A/D clock period,
t
ADCK
, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example,
if
the
system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000,
001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period
or greater than the maximum A/D clock period which may result in inaccurate A/D conversion
values. Refer to the following table for examples, where values marked with an asterisk * show
where, depending upon the device, special care must be taken, as the values may be exceeding the
specified A/D Clock Period range.
f
SYS
A/D Clock Period (t
ADCK
)
SACKS[2:0]
= 000
(f
SYS
)
SACKS[2:0]
= 001
(f
SYS
/2)
SACKS[2:0]
= 010
(f
SYS
/4)
SACKS[2:0]
= 011
(f
SYS
/8)
SACKS[2:0]
= 100
(f
SYS
/16)
SACKS[2:0]
= 101
(f
SYS
/32)
SACKS[2:0]
= 110
(f
SYS
/64)
SACKS[2:0]
= 111
(f
SYS
/128)
1MHz
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
128μs *
2MHz
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
4MHz
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
8MHz
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
A/D Clock Period Examples
