Rev. 1.10
110
November 04, 2019
Rev. 1.10
111
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I
2
C interface. This uses
the internal clock to in effect add a debounce time to the external clock to reduce the possibility
of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve the required I
2
C data transfer speed, there
exists a relationship between the system clock, f
SYS
, and the I
2
C debounce time. For either the I
2
C
Standard or Fast mode operation, users must take care of the selected system clock frequency and
the configured debounce time to match the criterion shown in the following table.
I
2
C Debounce Time Selection I
2
C Standard Mode (100kHz)
I
2
C Fast Mode (400kHz)
No Debounce
f
SYS
> 2MHz
f
SYS
> 5MHz
2 system clock debounce
f
SYS
> 4MHz
f
SYS
> 10MHz
4 system clock debounce
f
SYS
> 8MHz
f
SYS
> 20MHz
I
2
C Minimum f
SYS
Frequency Requirement
I
2
C Registers
There are three control registers associated with the I
2
C bus, SIMC0, SIMC1 and SIMTOC, one
address register SIMA and one data register, SIMD. Note that the SIMC1, SIMD, SIMA and
SIMTOC registers and their POR values are only available when the I
2
C mode is selected by
properly configuring the UMD and SIM2~SIM0 bits in the SIMC0 register.
Register
Name
Bit
7
6
5
4
3
2
1
0
SIMC0
SIM2
SIM1
SIM0
UMD
SIMDEB1 SIMDEB0 SIMEN
SIMICF
SIMC1
HCF
HAAS
HBB
HTX
TXAK
SRW
IAMWU
RXAK
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SIMA
SIMA6
SIMA5
SIMA4
SIMA3
SIMA2
SIMA1
SIMA0
D0
SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
I
2
C Register List
I
2
C Data Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I
2
C functions. Before the device writes data to the I
2
C bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the I
2
C bus, the
device can read it from the SIMD register. Any transmission or reception of data from the I
2
C bus
must be made via the SIMD register.
• SIMD Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Bit 7~0
D7~D0
: USIM SPI/I
2
C data register bit 7 ~ bit 0
I
2
C Address Register
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is
the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register
define the device slave address. Bit 0 is not defined. When a master device, which is connected to
the I
2
C bus, sends out an address, which matches the slave address in the SIMA register, the slave
device will be selected.