Rev. 1.10
128
November 04, 2019
Rev. 1.10
129
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
Receive Break
Any break character received by the UART will be managed as a framing error. The receiver
will count and expect a certain number of bit times as specified by the values programmed into
the UBNO bit plus one stop bit. If the break is much longer than 13 bit times, the reception will
be considered as complete after the number of bit times specified by UBNO plus one stop bit.
The URXIF bit is set, UFERR is set, zeros are loaded into the receive data register, interrupts are
generated if appropriate and the URIDLE bit is set. A break is regarded as a character that contains
only zeros with the UFERR flag set. If a long break signal has been detected, the receiver will regard
it as a data frame including a start bit, data bits and the invalid stop bit and the UFERR flag will be
set. The receiver must wait for a valid stop bit before looking for the next start bit. The receiver will
not make the assumption that the break condition on the line is the next start bit. The break character
will be loaded into the buffer and no further data will be received until stop bits are received. It
should be noted that the URIDLE read only flag will go high when the stop bits have not yet been
received. The reception of a break character on the UART registers will result in the following:
•
The framing error flag, UFERR, will be set.
•
The receive data register, UTXR_RXR, will be cleared.
•
The UOERR, UNF, UPERR, URIDLE or URXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit
and the reading of a stop bit, the receiver status flag in the UUSR register, otherwise known as the
URIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of
the next start bit, the URIDLE flag will have a high value, which indicates the receiver is in an idle
condition.
Receiver Interrupt
The read only receive interrupt flag URXIF in the UUSR register is set by an edge generated by the
receiver. An interrupt is generated if URIE=1, when a word is transferred from the Receive Shift
Register, RSR, to the Receive Data Register, UTXR_RXR. An overrun error can also generate an
interrupt if URIE=1.
Managing Receiver Errors
Several types of reception errors can occur within the UART module, the following section describes
the various types and how they are managed by the UART.
Overrun Error – UOERR
The UTXR_RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be
held in the FIFO register, while a third byte can continue to be received. Before this third byte has
been entirely shifted in, the data should be read from the UTXR_RXR register. If this is not done,
the overrun error flag UOERR will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
•
The UOERR flag in the UUSR register will be set.
•
The UTXR_RXR contents will not be lost.
•
The shift register will be overwritten.
•
An interrupt will be generated if the URIE bit is set.
The UOERR flag can be cleared by an access to the UUSR register followed by a read to the
UTXR_RXR register.
