Rev. 1.10
144
November 04, 2019
Rev. 1.10
145
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RX pin wake-up, can generate a USIM interrupt with the USIMF flag bit set high.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, and the Universal Serial Interface Module Interrupt enable bit, USIME, must first be set.
When the interrupt is enabled, the stack is not full and any of the above described situations occurs,
a subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced,
the Universal Serial Interface Module Interrupt flag, USIMF, will be automatically cleared. The EMI
bit will also be automatically cleared to disable other interrupts.
Note that if the USIM interrupt is triggered by the UART interface, after the interrupt has been
serviced, the UUSR register flags will only be cleared when certain actions are taken by the UART,
the details of which are given in the UART section.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pins may cause their respective interrupt flag to be set high and
consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are
to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt
request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt
enable bits have no effect on the interrupt wake-up function.
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flag, MFnF, will be
automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service routine.
To return from an interrupt subroutine, either an RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI bit high
to allow further interrupts. The RET instruction however only executes a return to the main program
leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.
