Rev. 1.00
214
September 11, 2018
Rev. 1.00
215
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
Skip if Data Memory is zero
2
Note
None
LSZA [m]
Skip if Data Memory is zero with data movement to ACC
2
Note
None
LSNZ [m]
Skip if Data Memory is not zero
2
Note
None
LSZ [m].i
Skip if bit i of Data Memory is zero
2
Note
None
LSNZ [m].i
Skip if bit i of Data Memory is not zero
2
Note
None
LSIZ [m]
Skip if increment Data Memory is zero
2
Note
None
LSDZ [m]
Skip if decrement Data Memory is zero
2
Note
None
LSIZA [m]
Skip if increment Data Memory is zero with result in ACC
2
Note
None
LSDZA [m]
Skip if decrement Data Memory is zero with result in ACC
2
Note
None
Table Read
LTABRD [m] Read table to TBLH and Data Memory
3
Note
None
LTABRDL [m] Read table (last page) to TBLH and Data Memory
3
Note
None
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data
Memory
3
Note
None
LITABRDL [m] Increment table pointer TBLP first and Read table (last page) to TBLH and
Data Memory
3
Note
None
Miscellaneous
LCLR [m]
Clear Data Memory
2
Note
None
LSET [m]
Set Data Memory
2
Note
None
LSWAP [m]
Swap nibbles of Data Memory
2
Note
None
LSWAPA [m] Swap nibbles of Data Memory with result in ACC
2
None
Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles
are required, if no skip takes place two cycles is required.
2. Any extended instruction which changes the contents of the PCL register will also require three cycles for
execution.