Rev. 1.00
124
September 11, 2018
Rev. 1.00
125
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
A/D Converter Operation
The START bit is used to start and reset the A/D converter. When the microcontroller sets this bit
from low to high and then low again, an analog to digital conversion cycle will be initiated.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in process or not. When the A/D converter is reset by setting the START bit from low
to high, the ADBZ flag will be cleared to "0". This bit will be automatically set to "1" by the
microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is
complete, the ADBZ will be cleared to "0". In addition, the corresponding A/D converter interrupt
request flag will be set in the interrupt control register, and if the interrupts are enabled, an
appropriate internal interrupt signal will be generated. This A/D converter internal interrupt signal
will direct the program flow to the associated A/D converter internal interrupt address for processing.
If the A/D converter internal interrupt is disabled, the microcontroller can be used to poll the ADBZ
bit in the SADC0 register to check whether it has been cleared as an alternative method of detecting
the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
SYS
, can be
chosen to be either f
SYS
or a subdivided version of f
SYS
. The division ratio value is determined by
the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D conversion clock source is
determined by the system clock f
SYS
, and by bits SACK
S
2~SACK
S
0, there are some limitations
on the maximum A/D conversion clock source speed that can be selected. As the recommended
value of permissible A/D conversion clock period, t
ADCK
, is from 0.5μs to 10μs, care must be taken
for system clock frequencies. For example, if the system clock operates at a frequency of 4MHz,
the SACK
S
2~SACK
S
0 bits should not be set to "000", "110" or "111". Doing so will give A/D
conversion clock periods that are less than the minimum A/D conversion clock period or greater than
the maximum A/D conversion clock period which may result in inaccurate A/D conversion values.
Refer to the following table for examples, where values marked with an asterisk * special care must
be taken.
f
SYS
A/D Conversion Clock Period (t
ADCK
)
SACKS
[2:0]=000
(f
SYS
)
SACKS
[2:0]=001
(f
SYS
/2)
SACKS
[2:0]=010
(f
SYS
/4)
SACKS
[2:0]=011
(f
SYS
/8)
SACKS
[2:0]=100
(f
SYS
/16)
SACKS
[2:0]=101
(f
SYS
/32)
SACKS
[2:0]=110
(f
SYS
/64)
SACKS
[2:0]=111
(f
SYS
/128)
1MHz
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
128μs*
2MHz
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
10.67μs*
16MHz
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
A/D Conversion Clock Period Examples
Controlling the power on/off function of the A/D conversion circuitry is implemented using the
ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ADCEN bit is set high to power on the A/D conversion internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no
pins are selected for use as A/D converter inputs by configuring the corresponding pin control bits,
if the ADCEN bit is high then some power will still be consumed. In power conscious applications
it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D
converter function is not being used.
