Rev. 1.00
108
September 11, 2018
Rev. 1.00
109
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
• PTMRPL Register
Bit
7
6
5
4
3
2
1
0
Name
PTRP7
PTRP6
PTRP5
PTRP4
PTRP3
PTRP2
PTRP1
PTRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTRP7~PTRP0
:
PTM CCRP Low Byte Register bit 7 ~ bit 0
PTM 10-bit CCRP bit 7 ~ bit 0
• PTMRPH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PTRP9
PTRP8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
PTRP9~PTRP8
:
PTM CCRP High Byte Register bit 1 ~ bit 0
PTM 10-bit CCRP bit 9 ~ bit 8
Periodic Type TM Operation Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register.
Compare Match Output Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to "0".
If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF
Hex, value, however here the PTMAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the PTM output pin will change
state. The PTM output pin condition however only changes state when a PTMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM
output pin. The way in which the PTM output pin changes state are determined by the condition of
the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the
PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after
the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and
PTIO0 bits are zero then no pin change will take place.
