Rev. 1.00
120
September 11, 2018
Rev. 1.00
121
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
• SADC1 Register
Bit
7
6
5
4
3
2
1
0
Name
SAINS3
SAINS2
SAINS1
SAINS0
—
SACKS2 SACKS1 SACKS0
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
0
0
—
0
0
0
Bit 7~4
SAINS3~SAINS0
: A/
D
converter input signal selection
0
000: External signal – External analog channel input, ANn
0
001: Internal signal – Internal A/D converter power supply voltage AV
DD
0
010: Internal signal – Internal A/D converter power supply voltage AV
DD
/2
0
011: Internal signal – Internal A/D converter power supply voltage AV
DD
/4
01
00: External signal – External analog channel input, ANn
0
101: Internal signal – Internal A/D converter PGA output voltage V
R
0
110: Internal signal – Internal A/D converter PGA output voltage V
R
/2
0
111: Internal signal – Internal A/D converter PGA output voltage V
R
/4
1000~1011: Reserved, connected to ground
1100~1111: External signal – External analog channel input, ANn
When the internal analog signal is selected to be converted, the external channel input
signal will automatically be switched off regardless of the SACS bit field value. It will
prevent the external channel input from being connected together with the internal
analog signal.
Bit 3
Unimplemented, read as "0"
Bit 2~0
SACKS2~SACKS0
: A/
D
conversion clock source selection
000: f
SYS
001: f
SYS
/2
010: f
SYS
/4
011: f
SYS
/8
100: f
SYS
/16
101: f
SYS
/32
110: f
SYS
/64
111: f
SYS
/128
• SADC2 Register
Bit
7
6
5
4
3
2
1
0
Name
ADPGAEN
—
—
PGAIS
SAVRS1 SAVRS0 PGAGS1 PGAGS0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
0
—
—
0
0
0
0
0
Bit 7
ADPGAEN
: A/D converter PGA enable/disable control
0: Disable
1: E
nable
When the PGA output V
R
is selected as A/D converter input or A/D converter
reference voltage, the PGA needs to be enabled by setting this bit high. Otherwise the
PGA needs to be disabled by clearing this bit to zero to conserve the power.
Bit 6~5
Unimplemented, read as "0"
Bit 4
PGAIS
: PGA input (V
RI
) selection
0: External VREFI pin
1: Internal reference voltage, V
BGREF
When the internal reference voltage V
BGREF
is selected as the PGA input, the external
reference voltage on the VREFI pin will be automatically switched off. When this bit
is set high to select V
BGREF
as PGA input, the internal bandgap reference V
BGREF
should
be enabled by setting the VBGREN bit in the VBGRC register to "1".