Rev. 1.00
140
September 11, 2018
Rev. 1.00
141
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
SPI Bus Enable/Disable
To enable the SPI bus, set CSEN=1 and SCS=0, then wait for data to be written into the SIMD
(TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX
buffer) register, then transmission or reception will start automatically. When all the data has been
transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK,
data in the TXRX buffer will be shifted out or data on SDI will be shifted in.
When the SPI bus is disabled, SCK, SDI, SDO and SCS can become I/O pins or other pin-shared
functions using the corresponding pin-shared control bits
.
SPI Operation Steps
All communication is carried out using the 4-line interface for either Master or Slave Mode.
The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this
bit high will enable the SPI interface by allowing the SCS
line to be active, which can then be used
to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS
line will be in a floating condition and can therefore not be used for control of the SPI interface.
If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a
floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low
depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode
the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled
and
SCS, SDI, SDO and SCK will all become I/O pins or the other functions using the corresponding
pin-shared control bits. In the Master Mode the Master will always generate the clock signal. The
clock and data transmission will be initiated after data has been written into the SIMD register.
In the Slave Mode, the clock signal will be received from an external master device for both data
transmission and reception. The following sequences show the order to be followed for data transfer
in both Master and Slave Mode
.
Master Mode
• Step 1
Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control
register
.
• Step 2
Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting
must be the same with the Slave devices.
• Step 3
Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface.
• Step 4
For write operations: write the data to the SIMD register, which will actually place the data into
the TXRX buffer. Then use the SCK and SCS
lines to output the data. After this, go to step
5.
For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SIMD register.
• Step 5
Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to
zero then go to the following step.
• Step 6
Check the TRF bit or wait for an SIM SPI serial bus interrupt.
• Step 7
Read data from the SIMD register.
