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Rev. 1.00
456 of 576
January 28, 2022
32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
21 Serial Peripheral Interface (SPI)
PDMA Interface (HT32F54243/HT32F54253 only)
The PDMA interface is integrated in the SPI module. The PDMA function can be enabled by
setting the TXDMAE or RXDMAE bit to 1 in the transmitter or receiver mode respectively. When
the transmit buffer empty flag, TXBE, is asserted and the TXDMAE bit is set to 1, the PDMA
function will be activated to move data from the memory location that users designated into the SPI
data register or the TX FIFO until the TXBE flag is cleared to 0. The TXBE flag will be asserted
when the transmit buffer is empty in the non-FIFO mode or the data contained in the TX FIFO is
equal to or less than the level defined by the TXFTLS field in the FIFO mode.
Similarly, when the receive buffer not empty flag, RXBNE, is asserted and the RXDMAE bit is set
to 1, the PDMA function will be activated to move data from the SPI data register or the RX FIFO
to the memory location that users designated until the RXBNE flag is cleared to 0. The RXBNE
flag will be asserted when the receive buffer is not empty in the non-FIFO mode or the data
contained in the RX FIFO is equal to or greater than the level defined by the RXFTLS field in the
FIFO mode.
For a more detailed description about the PDMA configurations, refer to the PDMA chapter.
Register Map
The following table shows the SPI registers and reset values. The PDMA related describes are only
available for the HT32F54243/HT32F54253 devices.
Table 53. SPI Register Map
Register
Offset
Description
Reset Value
SPICR0
0x000
SPI Control Register 0
0x0000_0000
SPICR1
0x004
SPI Control Register 1
0x0000_0000
SPIIER
0x008
SPI Interrupt Enable Register
0x0000_0000
SPICPR
0x00C
SPI Clock Prescaler Register
0x0000_0000
SPIDR
0x010
SPI Data Register
0x0000_0000
SPISR
0x014
SPI Status Register
0x0000_0003
SPIFCR
0x018
SPI FIFO Control Register
0x0000_0000
SPIFSR
0x01C
SPI FIFO Status Register
0x0000_0000
SPIFTOCR 0x020
SPI FIFO Time Out Counter Register
0x0000_0000