18
FinePix F601 Zoom (U/E/EG) SERVICE MANUAL
3.Schematic
3-3.
Primary Block Functions Description
3-3-1.
Technical Outline
The FinePix F601 incorporates a
3rd generation Super CCD Honeycomb
and a
new signal processing LSI (UCS,
IC204)
. The
signal processing LSI (UCS, IC204)
is equivalent to the
image signal processing IC (SCS3D, IC304,
CSP)
incorporated in the previous
FinePix6800Z
, however the new IC permits a dramatic reduction in the interval
between photography and playback.
Pixel addition processing*1
and noise reduction have produced the world’s
first compact camera capable of photography at ISO800/1600, and the camera also employs the ultra high-
sensitivity ‘candlelight shot’ useful in scenes at low light levels.
The 3rd generation Super CCD Honeycomb improves performance during movie photography. The new data
transfer method used permits
mixing*2 of horizontal and vertical pixels inside the CCD
to allow a VGA15 frame
in excess of three megapixels per second, a capability not supported in conventional cameras.
*1 Data obtained with honeycomb signal processing consists of approximately twice the effective number of pixels.
Every four of the pixels is consolidated into a single pixel to increase the signal level (sensitivity) by a factor of four, and
the S/N (signal to noise) ratio by a factor of two, and thus permit photography at up to ISO1600.
*2 Every two pixels on the vertical and horizontal axes of the CCD are mixed to increase the signal level by a factor of four,
and the S/N ratio by a factor of two. This produces movie images of high sensitivity and high quality, while at the same
time permitting high-speed retrieval, and allowing 30 VGA-size frames per second.
3-3-2.
Block Functions Descriptions
(1) CCD block (CCD signal processing) and CAM block (image circuit block)
g
The analog video signal from the CCD (1" x 1.7", 3,100,000 effective pixels, square pixel honeycomb array, primary
color CCD) is psuedo-color compensated (CDS), adaptively interpolated (CDS), amplified (AGC), and signals mixed
(CDS) in
the single-chip CSP IC (SCS3A, IC109)
, and converted (A/D) to a 12-bit digital signal (CSP IC - Chip Size
Package IC). The CSP IC also incorporates the TG/SSG function previously supported by a separate IC. The convert-
ed digital signal is sent to the
signal processing LSI (UCS, IC204)
.
g
This block also incorporates the CCD horizontal/vertical drive IC
(IC105)
.
(2) Motor Block
g
The
signal processing LSI (UCS, IC204)
receives commands from the switches, monitors the AF motor drive, shutter
drive, zoom motor drive, and iris motor drive (IC113), and controls each motor with the appropriate driver circuit.
(3) Process Block (image processing)
g
Input data from CCD
The 12-bit digital image data (1H equivalent) from the CCD CAM block is sent to the
signal processing LSI (UCS,
IC204)
, buffered in its internal buffer, and converted to 32-bit (16-bit x 2) data (CCD raw data). The 32-bit image data
(CCD raw data) is passed to the 32Mbyte
SDRAM (IC206)
via the I/O bus in the image signal processing IC. The
SDRAM temporarily stores a single frame equivalent (2832 pixels x 2128 lines). The 32-bit image data input to the
signal processing LSI (UCS, IC204)
is processed in the AUTO math processing block and sent to the
SCS3A IC
(IC109)
in the CAM block to obtain the appropriate AE, AWB, and AF.
g
Recording to SSFDC
The image data stored in the
SDRAM (IC206)
is passed one line at a time to the signal processing block via the I/O
bus in the
signal processing LSI (UCS, IC204)
. This data is unpacked (pre-processing consisting of conversion of 32-
bit data to 12-bit, digital clampimg, gamma compensation, and conversion of 12-bit R, G, and B data to 8-bit R, G, and
B data, followed by YC processing consisting of conversion of 8-bit digital R, B, and G signals to Y:Cb:Cr=4:2:2) in the
signal processing block, and 8-bit Y, Cr, and B image data is again sent to the internal buffer. The 8-bit Y:Cb:Cr
signals are sorted in the internal buffer into a format to suitable for DCT compression, and sent to the media controller
via the JPEG math block, and recorded in the SSFDC.
g
Image playback from SSFDC
The compressed image data from the SSFDC is sent to the
signal processing LSI (UCS, IC204)
as 8-bit image data
and sent to the
SDRAM (IC206)
via the media control unit, the DMA unit, and the internal bus control unit. The image
data temporarily stored in the
SDRAM (IC206)
is returned to the
signal processing LSI (UCS, IC204)
and sent to the
signal processing block via the media controller and JPEG math block. Post-processing involves conversion of the 8-
bit Y:Cr:Cb image signals to 8-bit R, G, and B signals in the image processing block, the text display signal being
overlaid simultaneously, and the data sent to the LCD block.
g
The image adjustment data is stored in
FLASH ROM (IC208)
.
(4) LCD Block (LCD control)
The R, G, and B digital signals input from the
signal processing LSI (UCS, IC204)
LCD block are sent directly to the
drive IC in the LCD monitor for use in LCD drive and gradation control for the LCD monitor.
(5) POWER ON Processing
The power switch is connected to the
POWER ON IC (IC353)
. When the power is switched on a ‘H’ signal is sent to the
POWER ON IC (IC353) SW1. The ‘H’ PWCTL signal is then sent to the DC/DC Block and the UCS system power
supply (3.3V, 1.5V) is then switched ON. The UCS then detects ‘H’ at the PWR_SW following reset, and the
PWR_ON_ACT signal is then output to ensure that the PWCTL signal output to the DC/DC Block by the POWER ON
IC is not set to ‘L’.
(6) DC/DC Block (power supply)
The power supply circuit on the DC board generates
1.5V
for the UCS (IC204),
3.3V
for the UCS (IC204), the FLASH
ROM (IC208), the SDRAM (IC206), the LED PWB, the MODE PWB, the SSFDC, the POWER ON IC (IC353), and STRB,
5V
for the EVR (IC207), the
CAM 3.3V
(CAM Block), the
EVF 3.3V
(EVF Block), the
MOT 3.3V
(MOTOR Block), the
MOT
5.6V
(MOTOR Block, BL Block, AUDIO Block),
-7.5V
for the CCD,
-10V
for the LCD monitor,
12V
for the BL Block,
15V
for the CCD and LCD monitor, and UNREG.
