5-3
Fuji Electric Co., Ltd.
MT6M12343 Rev.1.0
Dec.-2016
Chapter 5
Recommended wiring and layout
Vref=V
IS(ref)
R2
R2
R2
C2
C2
C2
COMP
COMP
COMP
OR
R1
R1
R1
C3
C3
C3
ZD1
ZD1
ZD1
C5
10k
Ω
+5V
Vcc
GND
MPU
ZD2
15V
M
C6
C1
C1
C4
C4
C4
Ns
VB(U)
11
10
9
5
3
21
20
19
18
17
16
15
14
13
12
22
23
24
26
28
30
36
32
U
P
V
W
N(V)
N(U)
N(W)
Vcc
IN
GND
OUT
Vs
Vcc
U
IN
V
IN
W
IN
U
OUT
V
OUT
W
OUT
Fo
IS
GND
VFO
IS
COM
COM
IN(LU)
IN(LV)
IN(LW)
V
CCL
V
CCH
IN(HU)
IN(HV)
IN(HW)
VB(V)
VB(W)
TEMP
NC
V
B
7
TEMP
Vcc
IN
GND
OUT
Vs
V
B
Vcc
IN
GND
OUT
Vs
V
B
3×HVIC
LVIC
3×BSD
6×IGBT 6×FWD
D1
D1
D1
<A>
<C>
<C>
<C>
<B>
<B>
<B>
Long GND wiring
here might
generate noise to
input and cause
IGBT malfunction.
Long wiring here
might cause OC
level fluctuation and
malfunction.
Long wiring here
might cause short
circuit failure,
wiring Inductance
should be less
than 10nH.
Bootstrap negative
electrodes should be
connected to U,V,W
terminals directly and
separated from the main
output wires
Bus voltage
(positive)
Bulk
capacitor
Bus voltage
(negative)
Fig. 5-2 Example of application circuit 2
(In case of sensing each phase current individually)
