QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-18
Freescale Semiconductor
2.3
Features Comparison
2.3.1
On-Chip Memory Comparison
2.3.2
Power-Saving Modes and Power-Saving Features Comparison
2.3.3
Package Comparison
Table 2-9. On-Chip Memory Comparison
MC9S08QE128
MCF51QE128
Peripheral register maps maintain relative addresses.
Up to 8 Kb of random-access memory (RAM).
FLASH read/program/erase over full operating voltage and temperature.
Up to 128KB of FLASH, two FLASH arrays of 64Kb x
8-bits arranged in series. Two flash arrays allow for
“read while write” programming.
Up to 128 KB of FLASH. Two FLASH arrays of 64 Kb x
8-bits arranged in parallel. FLASH “read while write” not
supported.
Security circuitry to prevent unauthorized access to
RAM and FLASH contents, default is secured when
blank
Security circuitry to prevent unauthorized access to
RAM and FLASH contents, default is unsecured when
blank
Table 2-10. Power-Saving mode Comparison
MC9S08QE128
MCF51QE128
Two very low power stop modes (Stop2 and Stop3).
Low Power run (LPRun) and wait (LPWait) modes allow for use of peripherals in reduced-current and
reduced-speed mode.
Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents.
Very low power external oscillator that can be used in stop modes to provide accurate clock source RTC module.
Very low power real time counter for use in run, wait, and stop modes with internal and external clock sources.
6µs typical wake up time from stop modes.
Reduced power wait mode (enabled by WAIT
instruction).
Reduced power wait mode (enabled by setting WAIT bit
in the SOPT1 register then executing STOP
instruction).
Table 2-11. Package Comparison
MC9S08QE128
MCF51QE128
Pin-to-pin compatible in 80-LQFP and 64-LQFP packages.
Additional 48-QFN, 44-QFP and 32-LQFP packages.
No additional packages.