QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-12
Freescale Semiconductor
2.2.2.2
Interrupt Sequence
The S08 core interrupt sequence first completes the current instruction then attends the requested interrupt.
The CPU responds to an interrupt with the same sequence operation as in a software interrupt (SWI), and
it differs from the address used for the vector retrieved.
Figure 2-16. The CPU Interrupt Sequence
2.2.3
ColdFire V1 or 9S08QE
The ColdFire V1 and S08 cores have significant differences, even though the 32 bit ColdFire V1 core
presents improvements in performance. These differences are highlighted in the following section.
The ColdFire V1 architecture features, staged pipelining allows the core to process multiple instructions
at the same time.
Store PCL in SP
Store X in SP
Store PCH in SP
Store A in SP
Store PCL in SP
Store CCR in SP
Sets the | bit in the CCR
Fetches the high-order
half of the interrupt
vector
Fetches the low-order
half of the interrupt
vector
Delays for one free bus
cycle
Init
1
Fetches three bytes of
program information
starting at the address
indicated by the interrupt
vector
Fills the instruction
queue, preparing for
execution of the first
instruction in the
interrupt service routine
1
2
2
End