QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor
2-5
Figure 2-8. Processor Status State Machine
Supervisor stack pointer (SSP) -- This ColdFire architecture supports two independent stack pointers,
A7 registers. Each operating mode has its own stack pointer, SSP and user
stack pointer (USP). The hardware implementation of these two registers do
not identify one as SSP and the other as USP. Instead, the hardware uses one
32-bit register as the active A7 and the other as, OTHER_A7.
System Byte
Condition Code Register (CCR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
T
0
S
M
0
I
0
0
0
X
N
Z
V
C
W
Figure 2-7. Status Register (SR)
Table 2-2. SR Field Descriptions
Field
Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14
Reserved, must be cleared.
13
S
Supervisor/user state.
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11
Reserved, must be cleared.
10–8
I
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
7–0
CCR
Refer to MCF51QE128 Reference Manual.
SR[S] = 1
SR[S] = 0
Reset
Supervisor
Mode
User Mode
Exception
Rte, move-to-sr with
sr_operand[13] = 1
Rte, move-to-sr with
sr_operand[13] = 0
