QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-4
Freescale Semiconductor
Figure 2-5. Program Counter Register (PC)
Condition code register (CCR) -- This register reflects the result of most instruction flags. It is used to
evaluate the instructions of the conditional branches.
Second, is the supervisor programming model. This is intended to be used only by system control software
to implement restricted operating system functions: I/O control, and memory management. In the
supervisor programming model all registers and features of the ColdFire processors can be accessed and
modified. This consists of registers available in user mode and the following control registers:
•
16-bit status register (SR).
•
32-bit supervisor stack pointer (SSP).
•
32-bit vector base register (VBR).
•
32-bit CPU configuration register (CPUCR).
Status register (SR) — This is a 16-bit register. It stores the processor status and includes the condition
code register (CCR). When it is used in user mode only the lower 8-bit can
be accessed. When used in supervisor mode the registers can be accessed.
If a supervisor instruction is executed in user mode it generates a privilege
violation exception.
Figure 2-8
shows the SR behavior in a state machine.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Address
W
7
6
5
4
3
2
1
0
R
0
0
0
X
N
Z
V
C
W
Figure 2-6. Condition Code Register (CCR)
Table 2-1. CCR Field Descriptions
Field
Description
7–5
Reserved, must be cleared.
4
X
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
3
N
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
2
Z
Zero condition code bit. Set if result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition, or if a borrow occurs in a
subtraction; otherwise cleared.
