QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor
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Figure 2-17. V1 Core Pipelines
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The V1 Coldfire core pipeline stages include the following:
— Two-stage instruction fetch pipeline (IPF) (plus instruction buffer stage)
— Instruction address generation (IAG) – Calculates the next prefetch address
— Instruction fetch cycle (IC) – Initiates prefetch on the processor’s local bus
— Instruction buffer (IB) – Buffer stage minimizes effects of fetch latency using fifo queue
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Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC) – Decodes instruction and fetches the required
components for effective address calculation, or the operand fetch cycle
— Address generation/execute cycle (AGEX) – Calculates operand address or executes the
instruction
ColdFire V1 core architecture -- Is an orthogonal architecture that has an advantage. It has 16 different
registers for operation that can be used instead of one. The ColdFire V1 core
processes more effectively the 32-bit length operations than the 8-bit core
version.
S08 core architecture -- Is accumulator based, almost all arithmetic and logical instructions use the
accumulator. The S08 can handle 32-bit length operations but requires more
cycles because it executes more instructions, taking more time.
The ColdFire MCU has two programming models with different privileges to control the system. These
programming models are similar to the administrator and user in windows. When the MCU is on the
