Embedded Solutions
Page 23 of 37
RL1_CHAN_0-7_FIFO
[0x0020, 4C, 78, A4, D0, FC, 128, 154] Write TX/Read RX FIFO Port
RX and TX FIFO Port
Data Bit
Description
31-0
FIFO data word
FIGURE 12
PMC-BISERIAL-III RL1 RX/TX FIFO PORT
This port is used to make single-word accesses into the TX and out of the RX FIFO.
RL1_CHAN_0-7_TX_AMT_LVL
[0x0024, 50, 7C, A8, D4, 100, 12C, 158] TX almost-empty level (read/write)
TX Almost-Empty Level Register
Data Bit
Description
31-16
Spare
15-0
TX FIFO Almost-Empty Level
FIGURE 13
PMC-BISERIAL-III RL1 TX ALMOST EMPTY LEVEL REGISTER
This read/write port accesses the transmitter almost-empty level register. When the
number of data words in the transmit data FIFO is equal or less than this value, the
almost-empty status bit will be set.
RL1_CHAN_0-7_RX_AFL_LVL
[0x0028, 54, 80, AC, D8, 104, 130, 15C] RX almost-full level (read/write)
RX Almost-Full Level Register
Data Bit
Description
31-16
Spare
15-0
RX FIFO Almost-Full Level
FIGURE 14
PMC-BISERIAL-III RL1 RX ALMOST FULL LEVEL REGISTER
This read/write port accesses the receiver almost-full level register. When the number
of data words in the receive data FIFO is equal or greater than this value, the almost-full
status bit will be set.
