Embedded Solutions
Page 7 of 37
FIGURE 2
PMC-BISERIAL-III RL1 BLOCK DIAGRAM
The PMC-BiSerial-III RL1 configuration is shown in figure 2. The protocol implemented
provides eight I/O channels each consisting of RS-485 transmit and receive data. The
on-board PLL is used to generate two clocks that can be independently selected by
each channel in the design. The PLL is programmable and uses a 40 MHz reference
oscillator to generate a wide range of frequencies. The UART interface uses a 16x
clock to detect received data bits. The interface can operate at up to 10 Mbits/second
using a 160 MHz clock.
Data for all channels is sent and received LSB first using a low start-bit and one or two
high stop-bits to separate data bytes. An optional parity bit following the eight data bits
can be configured to implement odd, even, mark (always high), or space (always low)
parity. The marking (idle) state of the interface is high.
Each channel can be configured for either half or full-duplex operation. In half-duplex
mode, the receiver data is read from the transmit I/O while the transmitter is in a high
impedance state. Pull-up/pull-down resistor packs have been installed on the eight
transmit I/O lines to provide a logic ‘1’ when the I/O is un-driven. This prevents glitching
