Embedded Solutions
Page 18 of 37
RL1_CHAN_0-7_STATUS
[0x0014, 40, 6C, 98, C4, F0, 11C, 148] Channel Status Read/Clear Latch Write Port
Channel Status Register
Data Bit
Description
31
Channel Interrupt Active
30-20
Spare
19
User Interrupt Condition Occurred
18
Receive FIFO Overflow Occurred
17
Receive Framing Error Occurred
16
Receive Parity Error Occurred
15
Read DMA Interrupt Occurred
14
Write DMA Interrupt Occurred
13
Read DMA Error Occurred
12
Write DMA Error Occurred
11
RX FIFO Almost Full Interrupt Occurred
10
TX FIFO Almost Empty Interrupt Occurred
9
Receive Done Interrupt Occurred
8
Transmit Done Interrupt Occurred
7
Receive Data Valid
6
Receive FIFO Full
5
Receive FIFO Almost Full
4
Receive FIFO Empty
3
Transmit Data Valid
2
Transmit FIFO Full
1
Transmit FIFO Almost Empty
0
Transmit FIFO Empty
FIGURE 7
PMC-BISERIAL-III RL1 CHANNEL STATUS PORT
Transmit FIFO Empty: When a one is read, the transmit data FIFO contains no data;
when a zero is read, there is at least one data word in the FIFO.
Transmit FIFO Almost Empty: When a one is read, the number of data words in the
transmit data FIFO is less than or equal to the value written to the
RL1_CHAN_TX_AMT_LVL register; when a zero is read, the FIFO level is more than
that value.
Transmit FIFO Full: When a one is read, the transmit data FIFO is full; when a zero is
read, there is room for at least one more data word in the FIFO.
Transmit Data Valid: When a one is read, there is a valid transmit data word in the
transmit holding register. This register is only loaded when the TX I/O is enabled and
transmit FIFO data has been loaded. This bit can be set even if the transmit FIFO is
