Embedded Solutions
Page 14 of 37
Register Definitions
RL1_BASE_CONTROL
[0x0000] Base Control Register (read/write)
Base Control Register
Data Bit
Description
31-20
Spare
19
PLL Sdata Output
18
PLL S2 Output
17
PLL Sclk Output
16
PLL Enable
15-0
Spare
FIGURE 4
PMC-BISERIAL-III RL1 BASE CONTROL REGISTER
All bits are active high and are reset on power-up or reset command, except PLL
enable, which defaults to enabled (high) on power-up or reset.
PLL Enable: When this bit is set to a one, the signals used to program and read the PLL
are enabled.
PLL Sclk/Sdata Output: These signals are used to program the PLL over the I
2
C serial
interface. Sclk is always an output whereas Sdata is bi-directional. This register is
where the Sdata output value is specified. When Sdata is an input it is read from the
User Switch Port.
PLL S2 Output: This is an additional control line to the PLL that can be used to select
additional pre-programmed frequencies.
